Searched full:apic (Results 1 – 25 of 45) sorted by relevance
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/Zephyr-latest/drivers/timer/ |
D | Kconfig.x86 | 27 bool "Local APIC timer" 32 Use the x86 local APIC in periodic mode as the system time 35 without complete APIC emulation). Modern hardware will work 39 bool "Local APIC timer using TSC deadline mode" 44 Extremely simple timer driver based the local APIC TSC 55 bool "Local APIC timer using TSC time source" 63 local APIC in one-shot mode as the timeout event source. 64 You must know the ratio of the TSC frequency to the local APIC 72 int "Local APIC timer IRQ" 75 This option specifies the IRQ used by the local APIC timer. [all …]
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D | apic_timer.c | 18 * This driver enables the local APIC as the Zephyr system timer. It supports 19 * legacy ("tickful") mode only. The driver will work with any APIC that has 20 * the ARAT "always running APIC timer" feature (CPUID 0x06, EAX bit 2). 29 * by the local APIC timer block (before it gets to the timer divider). 46 BUILD_ASSERT(CYCLES_PER_TICK >= 1, "APIC timer: bad CYCLES_PER_TICK");
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D | apic_tsc.c | 36 * APIC timer frequency. This can be found via CPUID 0x15 (n = EBX, m = EAX) 215 /* The Zephyr APIC API is... idiosyncratic. The timer is a in timer_irq() 217 * presented to the IO-APIC, they're indices into a register in timer_irq() 218 * array in the local APIC. By Zephyr convention they come in timer_irq() 219 * after all the external IO-APIC interrupts, but that number in timer_irq() 236 * confuses the APIC emulation and deadline interrupts don't in clear_tsc_adjust() 249 * prevent later MSR writes from reordering before the APIC in smp_timer_init()
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/Zephyr-latest/drivers/interrupt_controller/ |
D | Kconfig.loapic | 8 This option selects local APIC as the interrupt controller. 13 bool "Access local APIC in x2APIC mode" 15 If your local APIC supports x2APIC mode, turn this on. 25 by software), the local APIC will deliver a spurious-interrupt 40 bool "IO-APIC" 44 This option signifies that the target has an IO-APIC device. This 45 capability allows IO-APIC-dependent code to be included.
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D | intc_ioapic.c | 12 * @brief Intel IO APIC/xAPIC driver 14 * This module is a driver for the IO APIC/xAPIC (Advanced Programmable 16 * and P7 (Pentium4) family processors. The IO APIC/xAPIC is included 18 * may be required to enable the IO APIC/xAPIC in some chip sets. 20 * system, IO APIC can be used in either a uni-processor or multi-processor 21 * system. The IO APIC handles interrupts very differently than the 8259A. 23 * - Method of Interrupt Transmission. The IO APIC transmits interrupts 26 * - Interrupt Priority. The priority of interrupts in the IO APIC is 29 * - More Interrupts. The IO APIC supports a total of 24 interrupts. 31 * The IO APIC unit consists of a set of interrupt input signals, a 24-entry [all …]
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D | intc_loapic.c | 10 * driver for x86 CPU local APIC (as an interrupt controller) 29 /* Local APIC Version Register Bits */ 31 #define LOAPIC_VERSION_MASK 0x000000ff /* LO APIC Version mask */ 32 #define LOAPIC_MAXLVT_MASK 0x00ff0000 /* LO APIC Max LVT mask */ 33 #define LOAPIC_PENTIUM4 0x00000014 /* LO APIC in Pentium4 */ 34 #define LOAPIC_LVT_PENTIUM4 5 /* LO APIC LVT - Pentium4 */ 35 #define LOAPIC_LVT_P6 4 /* LO APIC LVT - P6 */ 36 #define LOAPIC_LVT_P5 3 /* LO APIC LVT - P5 */ 38 /* Local APIC Vector Table Bits */ 54 /* Local APIC Spurious-Interrupt Register Bits */ [all …]
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D | intc_ioapic_priv.h | 13 /* IO APIC direct register offsets */ 20 /* IO APIC indirect register offset */ 30 #define IOAPIC_DT_APIC 0x0 /* APIC serial bus */
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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
D | loapic.h | 16 /* Local APIC Register Offset */ 18 #define LOAPIC_ID 0x020 /* Local APIC ID Reg */ 19 #define LOAPIC_VER 0x030 /* Local APIC Version Reg */ 70 * @brief Read 64-bit value from the local APIC in x2APIC mode. 81 * @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode. 93 * @brief Read value from the local APIC using the default mode. 95 * Returns a 32-bit value read from the local APIC, using the access 112 * @brief Write 64-bit value to the local APIC in x2APIC mode. 124 * @brief Write 32-bit value to the local APIC in xAPIC (MMIO) mode. 137 * @brief Write 32-bit value to the local APIC using the default mode. [all …]
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/Zephyr-latest/dts/bindings/interrupt-controller/ |
D | intel,loapic.yaml | 1 description: Local Advanced Programmable Interrupt Controller (APIC)
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D | intel,ioapic.yaml | 1 description: Intel I/O Advanced Programmable Interrupt Controller (APIC)
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/Zephyr-latest/boards/intel/ish/ |
D | Kconfig.defconfig | 13 default 2000 if APIC_TIMER_TSC # APIC timer's frequency is 19.2 MHZ or 100 MHZ
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/Zephyr-latest/boards/acrn/acrn/ |
D | board_acrn.c | 7 /* Local APIC IDs for each logical CPU */
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/Zephyr-latest/boards/up-bridge-the-gap/up_squared/ |
D | Kconfig.defconfig | 12 # TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz
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/Zephyr-latest/boards/intel/ehl/ |
D | Kconfig.defconfig | 21 # TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
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/Zephyr-latest/tests/kernel/timer/timer_monotonic/ |
D | testcase.yaml | 9 kernel.timer.monotonic.apic.tsc:
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/Zephyr-latest/boards/up-bridge-the-gap/up_squared_pro_7000/ |
D | Kconfig.defconfig | 12 # TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
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/Zephyr-latest/boards/intel/adl/ |
D | Kconfig.defconfig | 10 # TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
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/Zephyr-latest/boards/intel/rpl/ |
D | Kconfig.defconfig | 11 # TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
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/Zephyr-latest/arch/x86/core/intel64/ |
D | smp.c | 35 * assumes the use of a local APIC (but there's no other mechanism).
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D | cpu.c | 22 * Map of CPU logical IDs to CPU local APIC IDs. By default, 102 x86_cpu_loapics[cpuboot->cpu_id], "APIC ID miss match!"); in z_x86_cpu_init()
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/Zephyr-latest/tests/arch/x86/info/src/ |
D | timer.c | 40 printk("TIMER: new local APIC"); in timer()
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D | acpi.c | 126 printk("\tCPU #%d: APIC ID 0x%02x\n", i, cpu->Id); in acpi()
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/Zephyr-latest/arch/x86/include/intel64/ |
D | kernel_arch_data.h | 34 extern uint8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */
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/Zephyr-latest/boards/qemu/x86/doc/ |
D | index.rst | 12 * Advanced Programmable Interrupt Controller (APIC) 29 | APIC | on-chip | interrupt controller |
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/Zephyr-latest/include/zephyr/acpi/ |
D | acpi.h | 285 * @brief Retrieve the 'n'th enabled local apic info. 288 * @return local apic info on success or NULL otherwise
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