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/Zephyr-latest/dts/bindings/clock/
Dst,stm32h7rs-pll-clock.yaml16 f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
17 f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
18 f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
19 f(PLL_Sx) = f(VCOx clock) / PLLSx -> pllx_s_ck
20 f(PLL_Tx) = f(VCOx clock) / PLLTx -> pllx_t_ck (only for PLL2)
22 with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
Dst,stm32h7-pll-clock.yaml17 f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
18 f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
19 f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
21 with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
48 Main PLL multiplication factor for VCOx
Dst,stm32wba-pll-clock.yaml22 Note: VCOx frequency range is 128 to 544 MHz. To reduce the power consumption,
Dst,stm32u5-pll-clock.yaml22 Note: To reduce the power consumption, it is recommended to configure the VCOx