Searched full:swdio (Results 1 – 25 of 39) sorted by relevance
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/Zephyr-latest/boards/wch/ch32v003f4p6_dev_board/ |
D | board.c | 22 * PD1 is wired to led and to SWDIO pin. in board_late_init_hook() 25 * If PD1 is put to ground, let the pin as SWDIO pin (default) to be in board_late_init_hook()
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/Zephyr-latest/dts/bindings/misc/ |
D | zephyr,swdp-gpio.yaml | 71 GPIO pin used for SWDIO input. This pin is also used for the SWDIO output 77 Optional GPIO pin used for SWDIO output. 82 GPIO pin used to disable the SWDIO output buffer behind optional
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/Zephyr-latest/boards/ruuvi/ruuvitag/doc/ |
D | index.rst | 66 * 19 = SWDIO 79 * 2 = SWDIO 92 * 2 = SWDIO 118 … to program the RuuviTag without the DEVKIT, this can be achieved via the SWDIO and SWDCLK pins lo…
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/Zephyr-latest/boards/seeed/wio_terminal/doc/ |
D | index.rst | 110 #. Solder cables to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, 115 :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the 116 Wio Terminal to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`,
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/Zephyr-latest/include/zephyr/drivers/ |
D | swdp.h | 46 * @brief Write count bits to SWDIO from data LSB first 58 * @brief Read count bits from SWDIO into data LSB first
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/Zephyr-latest/samples/subsys/dap/ |
D | README.rst | 17 The simplest configuration would be to connect ``SWDIO`` to ``dio``, ``SWDCLK`` to ``clk``
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/Zephyr-latest/boards/makerbase/mks_canable_v20/doc/ |
D | index.rst | 49 - SWDIO : PA13 67 MKS CANable V2.0 board includes an SWDIO debug connector header J4.
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/Zephyr-latest/boards/adafruit/feather_m4_express/doc/ |
D | index.rst | 133 :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the 134 Feather to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`,
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/Zephyr-latest/boards/adafruit/itsybitsy_m4_express/doc/ |
D | index.rst | 132 :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the 133 ItsyBitsy to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`,
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/Zephyr-latest/drivers/dp/ |
D | swdp_bitbang.c | 112 /* Set the SWDIO DAP hardware output pin to high level */ 132 /* Set the SWDIO DAP hardware output pin to low level */ 152 /* Set the SWDIO DAP hardware output pin to bit level */ 163 /* Return current level of the SWDIO DAP hardware input pin */ 176 * Configure the SWDIO DAP hardware to output mode. 199 * Configure the SWDIO DAP hardware to input mode.
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/Zephyr-latest/boards/ebyte/e73_tbb/doc/ |
D | index.rst | 106 | 4 | SWDIO | 143 To flash the board connect pins: SWDIO, SWDCLK, RST, GND from E73-TBB
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/Zephyr-latest/boards/gd/gd32f407v_start/doc/ |
D | index.rst | 63 (PA13/SWDIO and PA14/SWCLK in the JP6 header).
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/Zephyr-latest/boards/holyiot/yj16019/doc/ |
D | index.rst | 58 * SWDIO = SDO
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/Zephyr-latest/boards/wch/ch32v003f4p6_dev_board/doc/ |
D | index.rst | 59 reconnect the external debugger SWDIO pin to PD1/SWIO to be able to flash the board
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/Zephyr-latest/boards/vcc-gnd/yd_stm32h750vb/doc/ |
D | index.rst | 29 - LED_1 : PA13 (SWDIO)
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/Zephyr-latest/boards/ambiq/apollo3_evb/ |
D | apollo3_evb_connector.dtsi | 34 <21 0 &gpio0_31 21 0>, /* SWDIO */
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/Zephyr-latest/boards/seeed/lora_e5_dev_board/ |
D | lora_e5_dev_board.dts | 203 * Debug: PA13(swdio), PA14(swclk)
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/Zephyr-latest/boards/adi/max32660evsys/doc/ |
D | index.rst | 98 interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4).
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/Zephyr-latest/boards/ambiq/apollo3p_evb/ |
D | apollo3p_evb_connector.dtsi | 34 <21 0 &gpio0_31 21 0>, /* SWDIO */
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/Zephyr-latest/boards/ronoth/lodev/ |
D | ronoth_lodev.dts | 68 <14 0 &gpioa 13 0>, /* PA13 / SWDIO */
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/Zephyr-latest/boards/segger/trb_stm32f407/doc/ |
D | index.rst | 42 | 1 | VTref | 2 | SWDIO/TMS |
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/Zephyr-latest/boards/u-blox/ubx_evkninab1/ |
D | ubx_evkninab1_nrf52832.dts | 91 /* 11 SWDIO */ /* D5 */
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/Zephyr-latest/boards/waveshare/nrf51_ble400/doc/ |
D | index.rst | 123 * RESET = SWDIO
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/Zephyr-latest/boards/arduino/nano_33_ble/doc/ |
D | index.rst | 89 bit of difficult soldering. At a minimum, SWDIO and SWCLK need soldering (As
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/Zephyr-latest/boards/ronoth/lodev/doc/ |
D | index.rst | 76 15 PA13 SWDIO
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