1# Copyright (c) 2019 Phytec Messtechnik GmbH
2# Copyright (c) 2023 Nordic Semiconductor ASA
3# SPDX-License-Identifier: Apache-2.0
4
5description: |
6  This is a representation of the Serial Wire Debug Port interface
7  implementation by GPIO bit-banging.
8
9  Schematic using dual-supply bus transceiver and separate dout and dnoe pins
10
11         VCC_3V3                      VCC_REF
12            ^                           ^
13            |       +-------------+     |
14            +-------|vcca     vccb|-----+
15                    |             |
16   clk-gpios -------|a           b|-------------- SWD CLK
17                    |             |
18   noe-gpios -------|dir       gnd|-----+
19                    +-------------+     |
20                     74LVC1T45          v
21                                       GND
22
23
24         VCC_3V3                      VCC_REF
25            ^                           ^
26            |       +-------------+     |
27            +-------|vcca     vccb|-----+
28                    |             |
29   dio-gpios -------|a           b|------------*- SWD DIO
30                    |             |            |
31            +-------|dir       gnd|-----+      |
32            |       +-------------+     |      |
33            v        74LVC1T45          v      |
34           GND                         GND     |
35                                               |
36                                               |
37         VCC_3V3                      VCC_REF  |
38            ^                           ^      |
39            |       +-------------+     |      |
40            +-------|vcca     vccb|-----+      |
41                    |             |            |
42  dout-gpios -------|a           b|------------+
43                    |             |
44  dnoe-gpios -------|dir       gnd|-----+
45                    +-------------+     |
46                     74LVC1T45          v
47                                       GND
48
49  Direct connection using only dio pin for SWD DIO.
50
51   clk-gpios ------------------------------------ SWD CLK
52
53   dio-gpios ------------------------------------ SWD DIO
54
55  Of course, bidirectional bus transceiver between dio and SWD DIO can also be
56  used together with noe pin to enable/disable transceivers.
57
58compatible: "zephyr,swdp-gpio"
59
60include: base.yaml
61
62properties:
63  clk-gpios:
64    type: phandle-array
65    required: true
66    description: GPIO pin used for SWCLK output
67
68  dio-gpios:
69    type: phandle-array
70    required: true
71    description: |
72      GPIO pin used for SWDIO input. This pin is also used for the SWDIO output
73      if separate output pin is not defined.
74
75  dout-gpios:
76    type: phandle-array
77    description: |
78      Optional GPIO pin used for SWDIO output.
79
80  dnoe-gpios:
81    type: phandle-array
82    description: |
83      GPIO pin used to disable the SWDIO output buffer behind optional
84      pin dout-gpios.
85
86  noe-gpios:
87    type: phandle-array
88    description: |
89      Optional pin to disable all bus transceivers if any are present.
90
91  reset-gpios:
92    type: phandle-array
93    description: |
94      Optional GPIO pin used for RESET output.
95
96  port-write-cycles:
97    type: int
98    required: true
99    description: |
100      Number of processor cycles for I/O Port write operations.For example, the
101      GPIO clock may be different from the CPU clock. This can usually be
102      found in the SoC documentation.
103