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/Zephyr-latest/drivers/i2c/
Di2c_npcx_port.c11 * @brief Nuvoton NPCX smb/i2c port driver
23 * SDA_N Port 0----| |----| SMB/I2C |
110 /* Lock mutex of i2c/smb controller */ in i2c_npcx_port_transfer()
120 /* Unlock mutex of i2c/smb controller */ in i2c_npcx_port_transfer()
135 /* Lock mutex of i2c/smb controller */ in i2c_npcx_port_recover_bus()
140 /* Unlock mutex of i2c/smb controller */ in i2c_npcx_port_recover_bus()
Di2c_npcx_controller.c12 * @brief Nuvoton NPCX smb/i2c module (controller) driver
14 * This file contains the driver of SMB module (controller) which provides full
372 /* Enable SMB interrupt and 'New Address Match' interrupt source */ in i2c_ctrl_init_module()
503 * - Disable the SMB module first in i2c_ctrl_recovery()
1166 * suspend-to-idle stops SMB module clocks (derived from APB2/APB3), which must remain in npcx_i2c_ctrl_transfer()
1288 /* initialize mutex and semaphore for i2c/smb controller */ in i2c_ctrl_init()
Di2c_ite_it8xxx2.c402 /* Enable SMB channel in FIFO mode. */ in i2c_tran_fifo_write_start()
508 /* Enable SMB channel in FIFO mode. */ in i2c_tran_fifo_read_start()
1052 /* Disable SMB channels in FIFO mode. */ in i2c_it8xxx2_transfer()
/Zephyr-latest/drivers/smbus/
Dsmbus_utils.h100 * @brief Helper for handling an SMB alert
102 * This loops through all devices which triggered the SMB alert and
106 * @param callbacks list of SMB alert callbacks
Dsmbus_stm32.c47 LOG_DBG("%s: got SMB alert", dev->name); in smbus_stm32_smbalert_work()
111 LOG_DBG("%s: configuring SMB in host mode", dev->name); in smbus_stm32_configure()
114 LOG_DBG("%s: configuring SMB in device mode", dev->name); in smbus_stm32_configure()
119 LOG_DBG("%s: activating SMB alert", dev->name); in smbus_stm32_configure()
122 LOG_DBG("%s: deactivating SMB alert", dev->name); in smbus_stm32_configure()
Dintel_pch_smbus.h30 #define PCH_SMBUS_HSTS_SMB_ALERT BIT(5) /* SMB Alert */
/Zephyr-latest/dts/bindings/i2c/
Dene,kb1200-i2c.yaml4 description: ENE I2C/SMB controller
Dmicrochip,xec-i2c-v2.yaml4 description: Microchip I2C/SMB V2 controller
Dmicrochip,xec-i2c.yaml4 description: Microchip I2C/SMB controller
Dite,enhance-i2c.yaml35 The unit is number of SMB clock cycles. The time calculation
/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h1121 * SMBUS (SMB) device registers
1124 /* 0x000: SMB Serial Data */
1127 /* 0x002: SMB Status */
1130 /* 0x004: SMB Control Status */
1133 /* 0x006: SMB Control 1 */
1136 /* 0x008: SMB Own Address */
1139 /* 0x00A: SMB Control 2 */
1142 /* 0x00C: SMB Own Address */
1145 /* 0x00E: SMB Control 3 */
1147 /* 0x00F: SMB Bus Timeout */
[all …]
/Zephyr-latest/drivers/espi/
DKconfig.espi_emul16 number of required pins. It includes the functionality of LPC, SMB, SPI
/Zephyr-latest/subsys/mgmt/osdp/src/
Dosdp_pd.c581 uint8_t *smb = osdp_phy_packet_get_smb(pd, buf); in pd_build_reply() local
735 if (smb == NULL) { in pd_build_reply()
749 smb[0] = 3; /* length */ in pd_build_reply()
750 smb[1] = SCS_12; /* type */ in pd_build_reply()
751 smb[2] = ISSET_FLAG(pd, PD_FLAG_SC_USE_SCBKD) ? 0 : 1; in pd_build_reply()
755 if (smb == NULL) { in pd_build_reply()
765 smb[0] = 3; /* length */ in pd_build_reply()
766 smb[1] = SCS_14; /* type */ in pd_build_reply()
768 smb[2] = 1; /* CP auth succeeded */ in pd_build_reply()
777 smb[2] = 0; /* CP auth failed */ in pd_build_reply()
[all …]
Dosdp_cp.c132 uint8_t *smb = osdp_phy_packet_get_smb(pd, buf); in cp_build_command() local
297 if (smb == NULL) { in cp_build_command()
301 smb[0] = 3; /* length */ in cp_build_command()
302 smb[1] = SCS_11; /* type */ in cp_build_command()
303 smb[2] = ISSET_FLAG(pd, PD_FLAG_SC_USE_SCBKD) ? 0 : 1; in cp_build_command()
312 if (smb == NULL) { in cp_build_command()
317 smb[0] = 3; /* length */ in cp_build_command()
318 smb[1] = SCS_13; /* type */ in cp_build_command()
319 smb[2] = ISSET_FLAG(pd, PD_FLAG_SC_USE_SCBKD) ? 0 : 1; in cp_build_command()
331 if (smb && (smb[1] > SCS_14) && sc_is_active(pd)) { in cp_build_command()
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi51 i2c-smb-0 = &i2c_smb_0;
52 i2c-smb-1 = &i2c_smb_1;
53 i2c-smb-2 = &i2c_smb_2;
54 i2c-smb-3 = &i2c_smb_3;
55 i2c-smb-4 = &i2c_smb_4;
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c126 * SMB div = 1 (PLL / 2 = 24 mhz)
154 * SMB div = 3 (PLL / 4 = 24 mhz)
206 /* SSPI and SMB */ in chip_run_pll_sequence()
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_i2c_smb.h254 /* Offset 0x5C SMB Network layer FSM read-only */
/Zephyr-latest/soc/nuvoton/npcx/common/
Dregisters.c119 /* SMB register structure check */
/Zephyr-latest/soc/ite/ec/common/
Dchip_chipregs.h1298 * (1Cxxh) SMBus Interface (SMB) registers
/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst775 * NPCX simplified smb bank register usage