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/Zephyr-latest/drivers/spi/
DKconfig.psoc61 # Cypress SCB[SPI] configuration
7 bool "PSOC 6 MCU SCB spi driver"
13 This option enables the SCB[SPI] driver for PSOC 6 SoC family.
/Zephyr-latest/drivers/serial/
DKconfig.psoc61 # Cypress SCB[UART] configuration
8 bool "PSOC 6 MCU SCB serial driver"
16 This option enables the SCB[UART] driver for PSOC 6 SoC family.
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_03/
Dpsoc6_03.dtsi188 scb0: scb@40600000 {
189 compatible = "infineon,cat1-scb";
196 scb1: scb@40610000 {
197 compatible = "infineon,cat1-scb";
204 scb2: scb@40620000 {
205 compatible = "infineon,cat1-scb";
212 scb3: scb@40630000 {
213 compatible = "infineon,cat1-scb";
220 scb4: scb@40640000 {
221 compatible = "infineon,cat1-scb";
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_02/
Dpsoc6_02.dtsi202 scb0: scb@40600000 {
203 compatible = "infineon,cat1-scb";
210 scb1: scb@40610000 {
211 compatible = "infineon,cat1-scb";
218 scb2: scb@40620000 {
219 compatible = "infineon,cat1-scb";
226 scb3: scb@40630000 {
227 compatible = "infineon,cat1-scb";
234 scb4: scb@40640000 {
235 compatible = "infineon,cat1-scb";
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/
Dpsoc6_04.dtsi202 scb0: scb@40600000 {
203 compatible = "infineon,cat1-scb";
210 scb1: scb@40610000 {
211 compatible = "infineon,cat1-scb";
218 scb2: scb@40620000 {
219 compatible = "infineon,cat1-scb";
226 scb4: scb@40640000 {
227 compatible = "infineon,cat1-scb";
234 scb5: scb@40650000 {
235 compatible = "infineon,cat1-scb";
[all …]
/Zephyr-latest/arch/arm/core/cortex_m/
Dfault.c58 (uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) \
61 (uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) \
64 (uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) \
191 if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) { in mem_manage_fault()
196 if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) { in mem_manage_fault()
200 if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) { in mem_manage_fault()
211 uint32_t temp = SCB->MMFAR; in mem_manage_fault()
213 if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) { in mem_manage_fault()
218 SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk; in mem_manage_fault()
222 if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) { in mem_manage_fault()
[all …]
Dthread_abort.c43 SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; in z_impl_k_thread_abort()
49 SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk; in z_impl_k_thread_abort()
Dscb.c12 * Most of the SCB interface consists of simple bit-flipping methods, and is
13 * implemented as inline functions in scb.h. This module thus contains only data
123 if (SCB->CCR & SCB_CCR_DC_Msk) { in z_arm_init_arch_hw_at_boot()
Dprep_c.c57 SCB->VTOR = VECTOR_ADDRESS & VTOR_MASK; in relocate_vector_table()
90 SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk)); in z_arm_floating_point_init()
99 SCB->CPACR |= CPACR_CP10_FULL_ACCESS | CPACR_CP11_FULL_ACCESS; in z_arm_floating_point_init()
102 SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS; in z_arm_floating_point_init()
/Zephyr-latest/dts/bindings/arm/
Dinfineon,cat1-scb.yaml6 description: Infineon Serial Communication Blocks (SCB) node
8 compatible: "infineon,cat1-scb"
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_01/
Dpsoc6_01.dtsi217 scb0: scb@40610000 {
218 compatible = "infineon,cat1-scb";
225 scb1: scb@40620000 {
226 compatible = "infineon,cat1-scb";
233 scb2: scb@40630000 {
234 compatible = "infineon,cat1-scb";
241 scb3: scb@40640000 {
242 compatible = "infineon,cat1-scb";
249 scb4: scb@40650000 {
250 compatible = "infineon,cat1-scb";
[all …]
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dpower.c37 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pm_state_set()
60 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); in pm_state_exit_post_ops()
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dpower.c35 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pm_state_set()
57 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); in pm_state_exit_post_ops()
/Zephyr-latest/arch/arm/include/cortex_m/
Dexception.h173 SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk | in z_arm_exc_setup()
177 SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk; in z_arm_exc_setup()
179 SCB->BFAR = 0; in z_arm_exc_setup()
189 SCB->AIRCR = in z_arm_exc_setup()
190 (SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk))) in z_arm_exc_setup()
224 SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk | in z_arm_clear_faults()
229 SCB->HFSR = 0xffffffff; in z_arm_clear_faults()
/Zephyr-latest/dts/bindings/i2c/
Dinfineon,cat1-i2c.yaml9 This driver configures the SCB as an I2C device.
45 include: [i2c-controller.yaml, pinctrl-device.yaml, "infineon,cat1-scb.yaml"]
/Zephyr-latest/tests/arch/arm/arm_runtime_nmi/src/
Darm_runtime_nmi.c45 * State Register(ICSR) of System control block (SCB).
63 SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk; in ZTEST()
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dcyw20829.dtsi123 scb0: scb@40590000 {
124 compatible = "infineon,cat1-scb";
129 scb1: scb@405a0000 {
130 compatible = "infineon,cat1-scb";
135 scb2: scb@405b0000 {
136 compatible = "infineon,cat1-scb";
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_poweroff.c17 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in soc_core_sleepdeep_enable()
Dsoc_sam4l_poweroff.c17 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in soc_core_sleepdeep_enable()
/Zephyr-latest/modules/trusted-firmware-m/src/
Dreboot.c22 * the weak implementation of sys_arch_reboot() in scb.c.
/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
89 SCB->SCR &= ~BIT(2); in z_power_soc_deep_sleep()
129 SCB->SCR &= ~BIT(2); in z_power_soc_sleep()
/Zephyr-latest/dts/bindings/serial/
Dcypress,psoc6-uart.yaml5 description: Cypress SCB[UART]
Dinfineon,cat1-uart.yaml12 include: [uart-controller.yaml, pinctrl-device.yaml, "infineon,cat1-scb.yaml"]
/Zephyr-latest/soc/infineon/cat3/xmc4xxx/
Dsoc.c26 SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk; in soc_reset_hook()
/Zephyr-latest/soc/microchip/mec/mec15xx/
Ddevice_power.c41 SCB->SCR &= ~(1ul << 2); in soc_lite_sleep_enable()
52 SCB->SCR = (1ul << 2); /* Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_enable()
65 SCB->SCR &= ~(1ul << 2); /* disable Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_disable()

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