1# Copyright (c) 2018, Cypress
2# Copyright (c) 2020, ATL Electronics
3# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
4# an affiliate of Cypress Semiconductor Corporation
5#
6# SPDX-License-Identifier: Apache-2.0
7
8description: Infineon CAT1 UART
9
10compatible: "infineon,cat1-uart"
11
12include: [uart-controller.yaml, pinctrl-device.yaml, "infineon,cat1-scb.yaml"]
13
14properties:
15  reg:
16    required: true
17
18  interrupts:
19    required: true
20
21  pinctrl-0:
22    description: |
23      PORT pin configuration for TX, RX, RTS, CTS signals.
24      We expect that the phandles will reference pinctrl nodes. These
25      nodes will have a nodelabel that matches the Infineon SoC Pinctrl
26      defines and be of the form p<port>_<pin><peripheral inst>_<signal>.
27
28      Examples
29         use TX, RX
30         pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
31
32         use RX only
33         pinctrl-0 = <&p5_0_scb5_uart_rx>;
34
35         use TX, RX, RTS, CTS
36         pinctrl-0 = <&p3_1_scb2_uart_tx &p3_0_scb2_uart_rx
37                      &p3_2_scb2_uart_rts &p3_3_scb2_uart_cts>;
38    required: true
39
40  pinctrl-names:
41    required: true
42