| /Zephyr-latest/drivers/display/ |
| D | display_ili9341.c | 18 const struct ili9341_regs *regs = config->regs; in ili9341_regs_init() local
22 LOG_HEXDUMP_DBG(regs->pwseqctrl, ILI9341_PWSEQCTRL_LEN, "PWSEQCTRL"); in ili9341_regs_init()
23 r = ili9xxx_transmit(dev, ILI9341_PWSEQCTRL, regs->pwseqctrl, ILI9341_PWSEQCTRL_LEN); in ili9341_regs_init()
28 LOG_HEXDUMP_DBG(regs->timctrla, ILI9341_TIMCTRLA_LEN, "TIMCTRLA"); in ili9341_regs_init()
29 r = ili9xxx_transmit(dev, ILI9341_TIMCTRLA, regs->timctrla, ILI9341_TIMCTRLA_LEN); in ili9341_regs_init()
34 LOG_HEXDUMP_DBG(regs->timctrlb, ILI9341_TIMCTRLB_LEN, "TIMCTRLB"); in ili9341_regs_init()
35 r = ili9xxx_transmit(dev, ILI9341_TIMCTRLB, regs->timctrlb, ILI9341_TIMCTRLB_LEN); in ili9341_regs_init()
40 LOG_HEXDUMP_DBG(regs->pumpratioctrl, ILI9341_PUMPRATIOCTRL_LEN, "PUMPRATIOCTRL"); in ili9341_regs_init()
41 r = ili9xxx_transmit(dev, ILI9341_PUMPRATIOCTRL, regs->pumpratioctrl, in ili9341_regs_init()
47 LOG_HEXDUMP_DBG(regs->pwctrla, ILI9341_PWCTRLA_LEN, "PWCTRLA"); in ili9341_regs_init()
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| D | display_ili9342c.c | 19 const struct ili9342c_regs *regs = config->regs; in ili9342c_regs_init() local
23 LOG_HEXDUMP_DBG(regs->setextc, ILI9342C_SETEXTC_LEN, "SETEXTC"); in ili9342c_regs_init()
24 r = ili9xxx_transmit(dev, ILI9342C_SETEXTC, regs->setextc, in ili9342c_regs_init()
30 LOG_HEXDUMP_DBG(regs->gamset, ILI9342C_GAMSET_LEN, "GAMSET"); in ili9342c_regs_init()
31 r = ili9xxx_transmit(dev, ILI9342C_GAMSET, regs->gamset, in ili9342c_regs_init()
37 LOG_HEXDUMP_DBG(regs->ifmode, ILI9342C_IFMODE_LEN, "IFMODE"); in ili9342c_regs_init()
38 r = ili9xxx_transmit(dev, ILI9342C_IFMODE, regs->ifmode, in ili9342c_regs_init()
44 LOG_HEXDUMP_DBG(regs->frmctr1, ILI9342C_FRMCTR1_LEN, "FRMCTR1"); in ili9342c_regs_init()
45 r = ili9xxx_transmit(dev, ILI9342C_FRMCTR1, regs->frmctr1, in ili9342c_regs_init()
51 LOG_HEXDUMP_DBG(regs->invtr, ILI9342C_INVTR_LEN, "INVTR"); in ili9342c_regs_init()
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| D | display_ili9340.c | 16 const struct ili9340_regs *regs = config->regs; in ili9340_regs_init() local
20 LOG_HEXDUMP_DBG(regs->gamset, ILI9340_GAMSET_LEN, "GAMSET"); in ili9340_regs_init()
21 r = ili9xxx_transmit(dev, ILI9340_GAMSET, regs->gamset, in ili9340_regs_init()
27 LOG_HEXDUMP_DBG(regs->frmctr1, ILI9340_FRMCTR1_LEN, "FRMCTR1"); in ili9340_regs_init()
28 r = ili9xxx_transmit(dev, ILI9340_FRMCTR1, regs->frmctr1, in ili9340_regs_init()
34 LOG_HEXDUMP_DBG(regs->disctrl, ILI9340_DISCTRL_LEN, "DISCTRL"); in ili9340_regs_init()
35 r = ili9xxx_transmit(dev, ILI9340_DISCTRL, regs->disctrl, in ili9340_regs_init()
41 LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9340_PWCTRL1_LEN, "PWCTRL1"); in ili9340_regs_init()
42 r = ili9xxx_transmit(dev, ILI9340_PWCTRL1, regs->pwctrl1, in ili9340_regs_init()
48 LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9340_PWCTRL2_LEN, "PWCTRL2"); in ili9340_regs_init()
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| D | display_ili9488.c | 16 const struct ili9488_regs *regs = config->regs; in ili9488_regs_init() local
20 LOG_HEXDUMP_DBG(regs->frmctr1, ILI9488_FRMCTR1_LEN, "FRMCTR1"); in ili9488_regs_init()
21 r = ili9xxx_transmit(dev, ILI9488_FRMCTR1, regs->frmctr1, in ili9488_regs_init()
27 LOG_HEXDUMP_DBG(regs->disctrl, ILI9488_DISCTRL_LEN, "DISCTRL"); in ili9488_regs_init()
28 r = ili9xxx_transmit(dev, ILI9488_DISCTRL, regs->disctrl, in ili9488_regs_init()
34 LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9488_PWCTRL1_LEN, "PWCTRL1"); in ili9488_regs_init()
35 r = ili9xxx_transmit(dev, ILI9488_PWCTRL1, regs->pwctrl1, in ili9488_regs_init()
41 LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9488_PWCTRL2_LEN, "PWCTRL2"); in ili9488_regs_init()
42 r = ili9xxx_transmit(dev, ILI9488_PWCTRL2, regs->pwctrl2, in ili9488_regs_init()
48 LOG_HEXDUMP_DBG(regs->vmctrl, ILI9488_VMCTRL_LEN, "VMCTRL"); in ili9488_regs_init()
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| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_xtensa.h | 17 * This function loads ALL floating point registers pointed to by @a regs.
29 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
31 __asm__ volatile("wfr f0, %0\n" :: "r"(regs->fp_non_volatile.reg[0])); in _load_all_float_registers()
32 __asm__ volatile("wfr f1, %0\n" :: "r"(regs->fp_non_volatile.reg[1])); in _load_all_float_registers()
33 __asm__ volatile("wfr f2, %0\n" :: "r"(regs->fp_non_volatile.reg[2])); in _load_all_float_registers()
34 __asm__ volatile("wfr f3, %0\n" :: "r"(regs->fp_non_volatile.reg[3])); in _load_all_float_registers()
35 __asm__ volatile("wfr f4, %0\n" :: "r"(regs->fp_non_volatile.reg[4])); in _load_all_float_registers()
36 __asm__ volatile("wfr f5, %0\n" :: "r"(regs->fp_non_volatile.reg[5])); in _load_all_float_registers()
37 __asm__ volatile("wfr f6, %0\n" :: "r"(regs->fp_non_volatile.reg[6])); in _load_all_float_registers()
38 __asm__ volatile("wfr f7, %0\n" :: "r"(regs->fp_non_volatile.reg[7])); in _load_all_float_registers()
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| D | float_regs_arm_gcc.h | 20 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
25 : : "r" (®s->fp_volatile), "r" (®s->fp_non_volatile) in _load_all_float_registers()
29 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
34 : : "r" (®s->fp_volatile), "r" (®s->fp_non_volatile) in _store_all_float_registers()
39 static inline void _load_then_store_all_float_registers(struct fp_register_set *regs) in _load_then_store_all_float_registers() argument
41 _load_all_float_registers(regs); in _load_then_store_all_float_registers()
42 _store_all_float_registers(regs); in _load_then_store_all_float_registers()
51 * This function loads ALL floating point registers pointed to by @a regs.
64 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
69 : : "r" (®s->fp_volatile), "r" (®s->fp_non_volatile) in _load_all_float_registers()
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_grgpio2.c | 27 volatile struct grgpio_regs *regs; member
47 volatile struct grgpio_regs *regs = cfg->regs; in pin_configure() local
75 regs->output_or = mask; in pin_configure()
77 regs->output_and = ~mask; in pin_configure()
79 regs->dir_or = mask; in pin_configure()
82 regs->dir_and = ~mask; in pin_configure()
92 *value = cfg->regs->data; in port_get_raw()
102 volatile struct grgpio_regs *regs = cfg->regs; in port_set_masked_raw() local
108 port_val = (regs->output & ~mask) | value; in port_set_masked_raw()
109 regs->output = port_val; in port_set_masked_raw()
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| D | gpio_numicro.c | 31 GPIO_T *regs; member
53 GPIO_T * const regs = cfg->regs; in gpio_numicro_configure() local
103 regs->MODE = (regs->MODE & ~MODE_MASK(pin)) | in gpio_numicro_configure()
105 regs->DBEN = (regs->DBEN & ~BIT(pin)) | (debounce_enable << pin); in gpio_numicro_configure()
106 regs->SMTEN = (regs->SMTEN & ~BIT(pin)) | (schmitt_enable << pin); in gpio_numicro_configure()
107 regs->DINOFF = (regs->DINOFF & ~DINOFF_MASK(pin)) | in gpio_numicro_configure()
109 regs->PUSEL = (regs->PUSEL & ~PUSEL_MASK(pin)) | in gpio_numicro_configure()
119 *value = cfg->regs->PIN & PORT_PIN_MASK; in gpio_numicro_port_get_raw()
130 cfg->regs->DATMSK = ~mask; in gpio_numicro_port_set_masked_raw()
131 cfg->regs->DOUT = value; in gpio_numicro_port_set_masked_raw()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sam0_tc.c | 33 Tc *regs; member
53 static void wait_synchronization(Tc *regs, uint8_t counter_size) in wait_synchronization() argument
56 while (regs->COUNT8.SYNCBUSY.reg != 0) { in wait_synchronization()
59 while (regs->COUNT16.SYNCBUSY.reg != 0) { in wait_synchronization()
82 Tc *regs = cfg->regs; in pwm_sam0_set_cycles() local
101 inverted = ((regs->COUNT8.DRVCTRL.vec.INVEN & invert_mask) != 0); in pwm_sam0_set_cycles()
102 regs->COUNT8.CCBUF[channel].reg = TC_COUNT8_CCBUF_CCBUF(pulse_cycles); in pwm_sam0_set_cycles()
103 regs->COUNT8.PERBUF.reg = TC_COUNT8_PERBUF_PERBUF(period_cycles); in pwm_sam0_set_cycles()
104 wait_synchronization(regs, counter_size); in pwm_sam0_set_cycles()
107 regs->COUNT8.CTRLA.bit.ENABLE = 0; in pwm_sam0_set_cycles()
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| D | pwm_sam0_tcc.c | 22 Tcc *regs; member
40 static void wait_synchronization(Tcc *regs) in wait_synchronization() argument
42 while (regs->SYNCBUSY.reg != 0) { in wait_synchronization()
64 Tcc *regs = cfg->regs; in pwm_sam0_set_cycles() local
68 bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0); in pwm_sam0_set_cycles()
83 regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles); in pwm_sam0_set_cycles()
84 regs->PERBUF.reg = TCC_PERBUF_PERBUF(period_cycles); in pwm_sam0_set_cycles()
87 regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles); in pwm_sam0_set_cycles()
88 regs->PERB.reg = TCC_PERB_PERB(period_cycles); in pwm_sam0_set_cycles()
92 regs->CTRLA.bit.ENABLE = 0; in pwm_sam0_set_cycles()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_mchp_xec.c | 24 struct wdt_regs *regs; member
38 struct wdt_regs *regs = cfg->regs; in wdt_xec_setup() local
40 if (regs->CTRL & MCHP_WDT_CTRL_EN) { in wdt_xec_setup()
55 regs->CTRL |= MCHP_WDT_CTRL_JTAG_STALL_EN; in wdt_xec_setup()
57 regs->CTRL &= ~MCHP_WDT_CTRL_JTAG_STALL_EN; in wdt_xec_setup()
60 regs->CTRL |= MCHP_WDT_CTRL_EN; in wdt_xec_setup()
71 struct wdt_regs *regs = cfg->regs; in wdt_xec_disable() local
73 if (!(regs->CTRL & MCHP_WDT_CTRL_EN)) { in wdt_xec_disable()
77 regs->CTRL &= ~MCHP_WDT_CTRL_EN; in wdt_xec_disable()
90 struct wdt_regs *regs = cfg->regs; in wdt_xec_install_timeout() local
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32f1x.c | 48 static int is_flash_locked(FLASH_TypeDef *regs) in is_flash_locked() argument
50 return !!(regs->CR & FLASH_CR_LOCK); in is_flash_locked()
53 static void write_enable(FLASH_TypeDef *regs) in write_enable() argument
55 regs->CR |= FLASH_CR_PG; in write_enable()
58 static void write_disable(FLASH_TypeDef *regs) in write_disable() argument
60 regs->CR &= (~FLASH_CR_PG); in write_disable()
63 static void erase_page_begin(FLASH_TypeDef *regs, unsigned int page) in erase_page_begin() argument
66 regs->CR |= FLASH_CR_PER; in erase_page_begin()
67 regs->AR = FLASH_STM32_BASE_ADDRESS + page * FLASH_PAGE_SIZE; in erase_page_begin()
72 regs->CR |= FLASH_CR_STRT; in erase_page_begin()
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| D | flash_stm32l4x.c | 36 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
38 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
39 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
43 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
44 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
45 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
48 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
49 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
54 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
55 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32f2x.c | 25 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
30 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
31 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
35 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
36 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
37 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
43 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
44 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
49 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
50 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32g4x.c | 52 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
54 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
55 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
59 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
60 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
61 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
64 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
65 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
70 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
71 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32f4x.c | 46 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_valid_range() local
50 if (regs->OPTCR & FLASH_OPTCR_DB1M) { in flash_stm32_valid_range()
59 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
61 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
62 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
66 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
67 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
68 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
71 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
72 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
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| D | flash_stm32.c | 124 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_flush_caches()
126 if (regs->ACR & FLASH_ACR_DCEN) { in flash_stm32_flush_caches()
127 regs->ACR &= ~FLASH_ACR_DCEN; in flash_stm32_flush_caches()
128 regs->ACR |= FLASH_ACR_DCRST; in flash_stm32_flush_caches()
129 regs->ACR &= ~FLASH_ACR_DCRST; in flash_stm32_flush_caches()
130 regs->ACR |= FLASH_ACR_DCEN; in flash_stm32_flush_caches()
233 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_write_protection() local
247 regs->NSCR |= FLASH_STM32_NSLOCK; in flash_stm32_write_protection()
249 if (regs->NSCR & FLASH_STM32_NSLOCK) { in flash_stm32_write_protection()
250 regs->NSKEYR = FLASH_KEY1; in flash_stm32_write_protection()
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| /Zephyr-latest/drivers/sdhc/ |
| D | intel_emmc_host.c | 60 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in enable_interrupts() local
62 regs->normal_int_stat_en = EMMC_HOST_NORMAL_INTR_MASK; in enable_interrupts()
63 regs->err_int_stat_en = EMMC_HOST_ERROR_INTR_MASK; in enable_interrupts()
64 regs->normal_int_signal_en = EMMC_HOST_NORMAL_INTR_MASK; in enable_interrupts()
65 regs->err_int_signal_en = EMMC_HOST_ERROR_INTR_MASK; in enable_interrupts()
66 regs->timeout_ctrl = EMMC_HOST_MAX_TIMEOUT; in enable_interrupts()
71 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in disable_interrupts() local
74 regs->normal_int_stat_en = EMMC_HOST_NORMAL_INTR_MASK; in disable_interrupts()
75 regs->err_int_stat_en = EMMC_HOST_ERROR_INTR_MASK; in disable_interrupts()
78 regs->normal_int_signal_en &= 0; in disable_interrupts()
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| /Zephyr-latest/drivers/pcie/host/ |
| D | vc.c | 14 uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs) in pcie_vc_cap_lookup() argument
26 regs->cap_reg_1.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
28 regs->cap_reg_2.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
30 regs->ctrl_reg.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
38 struct pcie_vc_resource_regs *regs, in pcie_vc_load_resources_regs() argument
44 regs->cap_reg.raw = in pcie_vc_load_resources_regs()
47 regs->ctrl_reg.raw = in pcie_vc_load_resources_regs()
50 regs->status_reg.raw = in pcie_vc_load_resources_regs()
53 regs++; in pcie_vc_load_resources_regs()
58 struct pcie_vc_regs *regs, in get_vc_registers() argument
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| /Zephyr-latest/drivers/eeprom/ |
| D | eeprom_mchp_xec.c | 66 struct eeprom_xec_regs * const regs; member
75 static void eeprom_xec_execute_reg_set(struct eeprom_xec_regs * const regs, in eeprom_xec_execute_reg_set() argument
84 regs->execute = temp; in eeprom_xec_execute_reg_set()
87 static uint8_t eeprom_xec_data_buffer_read(struct eeprom_xec_regs * const regs, in eeprom_xec_data_buffer_read() argument
96 *destination_ptr = regs->buffer[count]; in eeprom_xec_data_buffer_read()
103 static uint8_t eeprom_xec_data_buffer_write(struct eeprom_xec_regs * const regs, in eeprom_xec_data_buffer_write() argument
112 regs->buffer[count] = *source_ptr; in eeprom_xec_data_buffer_write()
119 static void eeprom_xec_wait_transfer_compl(struct eeprom_xec_regs * const regs) in eeprom_xec_wait_transfer_compl() argument
133 sts = XEC_EEPROM_STS_TRANSFER_COMPL & regs->status; in eeprom_xec_wait_transfer_compl()
140 regs->status = XEC_EEPROM_STS_TRANSFER_COMPL; in eeprom_xec_wait_transfer_compl()
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| /Zephyr-latest/drivers/espi/ |
| D | espi_saf_mchp_xec.c | 72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
85 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
89 static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
93 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
95 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
145 static void saf_protection_regions_init(MCHP_SAF_HW_REGS *regs) in saf_protection_regions_init() argument
151 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
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| /Zephyr-latest/drivers/peci/ |
| D | peci_mchp_xec.c | 47 struct peci_regs * const regs; member
132 static int check_bus_idle(struct peci_regs * const regs) in check_bus_idle() argument
140 while (!(regs->STATUS2 & MCHP_PECI_STS2_IDLE)) { in check_bus_idle()
156 struct peci_regs * const regs = cfg->regs; in peci_xec_configure() local
162 regs->CONTROL = MCHP_PECI_CTRL_PD; in peci_xec_configure()
166 regs->OPT_BIT_TIME_LSB = value & MCHP_PECI_OPT_BT_LSB_MASK; in peci_xec_configure()
167 regs->OPT_BIT_TIME_MSB = ((value >> OPT_BIT_TIME_MSB_OFS) & in peci_xec_configure()
171 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_configure()
179 struct peci_regs * const regs = cfg->regs; in peci_xec_disable() local
183 ret = check_bus_idle(regs); in peci_xec_disable()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xec_qmspi.c | 22 QMSPI_Type *regs; member
40 static inline uint32_t descr_rd(QMSPI_Type *regs, uint32_t did) in descr_rd() argument
42 uintptr_t raddr = (uintptr_t)regs + MCHP_QMSPI_DESC0_OFS + in descr_rd()
48 static inline void descr_wr(QMSPI_Type *regs, uint32_t did, uint32_t val) in descr_wr() argument
50 uintptr_t raddr = (uintptr_t)regs + MCHP_QMSPI_DESC0_OFS + in descr_wr()
56 static inline void txb_wr8(QMSPI_Type *regs, uint8_t data8) in txb_wr8() argument
58 REG8(®s->TX_FIFO) = data8; in txb_wr8()
61 static inline uint8_t rxb_rd8(QMSPI_Type *regs) in rxb_rd8() argument
63 return REG8(®s->RX_FIFO); in rxb_rd8()
72 static void qmspi_set_frequency(QMSPI_Type *regs, uint32_t freq_hz) in qmspi_set_frequency() argument
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| /Zephyr-latest/drivers/serial/ |
| D | uart_apbuart.c | 127 struct apbuart_regs *regs; member
147 volatile struct apbuart_regs *regs = (void *) config->regs; in apbuart_poll_out() local
151 while (regs->status & APBUART_STATUS_TF) { in apbuart_poll_out()
159 while (!(regs->status & APBUART_STATUS_HOLD_REGISTER_EMPTY)) { in apbuart_poll_out()
164 regs->data = x & 0xff; in apbuart_poll_out()
170 volatile struct apbuart_regs *regs = (void *) config->regs; in apbuart_poll_in() local
172 if ((regs->status & APBUART_STATUS_DR) == 0) { in apbuart_poll_in()
175 *c = regs->data & 0xff; in apbuart_poll_in()
183 volatile struct apbuart_regs *regs = (void *) config->regs; in apbuart_err_check() local
184 const uint32_t status = regs->status; in apbuart_err_check()
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| D | uart_wch_usart.c | 17 USART_TypeDef *regs; member
31 USART_TypeDef *regs = config->regs; in usart_wch_init() local
59 regs->BRR = divn; in usart_wch_init()
60 regs->CTLR1 = ctlr1; in usart_wch_init()
61 regs->CTLR2 = 0; in usart_wch_init()
62 regs->CTLR3 = 0; in usart_wch_init()
75 USART_TypeDef *regs = config->regs; in usart_wch_poll_in() local
77 if ((regs->STATR & USART_STATR_RXNE) == 0) { in usart_wch_poll_in()
81 *ch = regs->DATAR; in usart_wch_poll_in()
88 USART_TypeDef *regs = config->regs; in usart_wch_poll_out() local
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