Lines Matching full:regs
72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
85 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
89 static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
93 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
95 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
145 static void saf_protection_regions_init(MCHP_SAF_HW_REGS *regs) in saf_protection_regions_init() argument
151 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
152 regs->SAF_PROT_RG[0].LIMIT = in saf_protection_regions_init()
153 regs->SAF_FL_CFG_SIZE_LIM >> 12; in saf_protection_regions_init()
154 regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL; in saf_protection_regions_init()
155 regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL; in saf_protection_regions_init()
157 regs->SAF_PROT_RG[n].START = in saf_protection_regions_init()
159 regs->SAF_PROT_RG[n].LIMIT = in saf_protection_regions_init()
161 regs->SAF_PROT_RG[n].WEBM = 0U; in saf_protection_regions_init()
162 regs->SAF_PROT_RG[n].RDBM = 0U; in saf_protection_regions_init()
165 LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START); in saf_protection_regions_init()
166 LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT); in saf_protection_regions_init()
167 LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM); in saf_protection_regions_init()
168 LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM); in saf_protection_regions_init()
211 QMSPI_Type *regs = (QMSPI_Type *)xcfg->qmspi_base_addr; in saf_qmspi_init() local
214 qmode = regs->MODE; in saf_qmspi_init()
219 qmode = regs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK); in saf_qmspi_init()
220 cstim = regs->CSTM; in saf_qmspi_init()
221 regs->MODE = MCHP_QMSPI_M_SRST; in saf_qmspi_init()
222 regs->STS = MCHP_QMSPI_STS_RW1C_MASK; in saf_qmspi_init()
227 regs->IFCTRL = in saf_qmspi_init()
232 regs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] = in saf_qmspi_init()
236 regs->IEN = MCHP_QMSPI_IEN_XFR_DONE; in saf_qmspi_init()
256 regs->MODE = qmode; in saf_qmspi_init()
257 regs->CSTM = cstim; in saf_qmspi_init()
275 static void saf_flash_timing_init(MCHP_SAF_HW_REGS *regs, in saf_flash_timing_init() argument
279 regs->SAF_POLL_TMOUT = cfg->poll_timeout; in saf_flash_timing_init()
280 regs->SAF_POLL_INTRVL = cfg->poll_interval; in saf_flash_timing_init()
281 regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval; in saf_flash_timing_init()
282 regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout; in saf_flash_timing_init()
283 regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay; in saf_flash_timing_init()
284 LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT); in saf_flash_timing_init()
285 LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL); in saf_flash_timing_init()
286 LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL); in saf_flash_timing_init()
287 LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT); in saf_flash_timing_init()
288 LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY); in saf_flash_timing_init()
294 static void saf_dnx_bypass_init(MCHP_SAF_HW_REGS *regs) in saf_dnx_bypass_init() argument
296 regs->SAF_DNX_PROT_BYP = 0; in saf_dnx_bypass_init()
297 regs->SAF_DNX_PROT_BYP = 0xffffffff; in saf_dnx_bypass_init()
346 static void saf_flash_misc_cfg(MCHP_SAF_HW_REGS *regs, uint8_t cs, in saf_flash_misc_cfg() argument
351 d = regs->SAF_FL_CFG_MISC; in saf_flash_misc_cfg()
377 regs->SAF_FL_CFG_MISC = d; in saf_flash_misc_cfg()
397 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr; in saf_flash_cfg() local
402 regs->SAF_CS_OP[cs].OPA = fcfg->opa; in saf_flash_cfg()
403 regs->SAF_CS_OP[cs].OPB = fcfg->opb; in saf_flash_cfg()
404 regs->SAF_CS_OP[cs].OPC = fcfg->opc; in saf_flash_cfg()
405 regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids; in saf_flash_cfg()
419 mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask); in saf_flash_cfg()
420 mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix); in saf_flash_cfg()
421 saf_flash_misc_cfg(regs, cs, fcfg); in saf_flash_cfg()
428 static void saf_tagmap_init(MCHP_SAF_HW_REGS *regs, in saf_tagmap_init() argument
435 regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i]; in saf_tagmap_init()
437 regs->SAF_TAG_MAP[i] = tag_map_dflt[i]; in saf_tagmap_init()
441 LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]); in saf_tagmap_init()
442 LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]); in saf_tagmap_init()
443 LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]); in saf_tagmap_init()
467 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr; in espi_saf_xec_configuration() local
475 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_configuration()
481 regs->SAF_CS0_CFG_P2M = 0; in espi_saf_xec_configuration()
482 regs->SAF_CS1_CFG_P2M = 0; in espi_saf_xec_configuration()
484 regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD; in espi_saf_xec_configuration()
488 regs->SAF_FL_CFG_THRH = totalsz; in espi_saf_xec_configuration()
503 regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1; in espi_saf_xec_configuration()
506 regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM); in espi_saf_xec_configuration()
508 saf_tagmap_init(regs, cfg); in espi_saf_xec_configuration()
510 saf_protection_regions_init(regs); in espi_saf_xec_configuration()
512 saf_dnx_bypass_init(regs); in espi_saf_xec_configuration()
514 saf_flash_timing_init(regs, xcfg); in espi_saf_xec_configuration()
528 regs->SAF_FL_CFG_MISC = in espi_saf_xec_configuration()
529 (regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u; in espi_saf_xec_configuration()
538 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC); in espi_saf_xec_configuration()
557 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr; in espi_saf_xec_set_pr() local
559 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_set_pr()
575 regs->SAF_PROT_RG[regnum].START = preg->start >> 12U; in espi_saf_xec_set_pr()
576 regs->SAF_PROT_RG[regnum].LIMIT = in espi_saf_xec_set_pr()
578 regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we; in espi_saf_xec_set_pr()
579 regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd; in espi_saf_xec_set_pr()
581 regs->SAF_PROT_RG[regnum].START = 0x7FFFFU; in espi_saf_xec_set_pr()
582 regs->SAF_PROT_RG[regnum].LIMIT = 0U; in espi_saf_xec_set_pr()
583 regs->SAF_PROT_RG[regnum].WEBM = 0U; in espi_saf_xec_set_pr()
584 regs->SAF_PROT_RG[regnum].RDBM = 0U; in espi_saf_xec_set_pr()
588 regs->SAF_PROT_LOCK |= (1UL << regnum); in espi_saf_xec_set_pr()
600 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr; in espi_saf_xec_channel_ready() local
602 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_channel_ready()
674 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr; in saf_ecp_access() local
681 if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) { in saf_ecp_access()
686 if (regs->SAF_ECP_BUSY & MCHP_SAF_ECP_BUSY) { in saf_ecp_access()
719 regs->SAF_ECP_INTEN = 0; in saf_ecp_access()
720 regs->SAF_ECP_STATUS = 0xffffffff; in saf_ecp_access()
729 regs->SAF_ECP_FLAR = pckt->flash_addr; in saf_ecp_access()
730 regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0]; in saf_ecp_access()
732 regs->SAF_ECP_CMD = in saf_ecp_access()
738 regs->SAF_ECP_START = MCHP_SAF_ECP_START; in saf_ecp_access()
745 xdat->hwstatus = regs->SAF_ECP_STATUS; in saf_ecp_access()
751 xdat->hwstatus = regs->SAF_ECP_STATUS; in saf_ecp_access()
755 regs->SAF_ECP_STATUS = xdat->hwstatus; in saf_ecp_access()
805 MCHP_SAF_HW_REGS *regs; in espi_saf_xec_activate() local
812 regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr; in espi_saf_xec_activate()
814 regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN; in espi_saf_xec_activate()