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/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_psram.overlay35 rx-inst-mode = "quad-spi";
36 rx-addr-mode = "quad-spi";
37 rx-data-mode = "quad-spi";
38 rx-dummy-mode = "quad-spi";
39 rx-extra-mode = "quad-spi";
40 tx-inst-mode = "quad-spi";
41 tx-addr-mode = "quad-spi";
42 tx-data-mode = "quad-spi";
/Zephyr-latest/arch/arm64/core/
Dheader.S29 .quad 0 // Image load offset from start
32 .quad _flash_used // Effective size of kernel
35 .quad HEADER_FLAGS // Informative flags,
38 .quad 0 // reserved
39 .quad 0 // reserved
40 .quad 0 // reserved
/Zephyr-latest/drivers/flash/
DKconfig.cadence_qspi_nor5 bool "Cadence Quad SPI Flash driver"
17 bool "Cadence Quad SPI Micron N25Q Support"
23 hex "Cadence Quad SPI subsector size"
26 Set the Cadence Quad SPI subsector size.
DKconfig.stm32_qspi1 # STM32 Quad SPI flash driver configuration options
10 bool "STM32 Quad SPI Flash driver"
DKconfig.nxp_s3225 - Quad Enable Requirements bitfield (DW15) must be present in the SFDP
26 tables to configure Quad mode. Otherwise it defaults to Dual or
/Zephyr-latest/drivers/sensor/adi/adltc2990/
DKconfig1 # ADLTC2990 Quad I2C Voltage, Current and Temperature sensor configuration options
7 bool "ADLTC2990 Quad I2C Voltage, Current and Temperature Monitor"
13 Quad I2C Voltage, Current and Temperature Monitor.
/Zephyr-latest/include/zephyr/drivers/flash/
Dnpcx_flash_api_ex.h27 * NPCX Configure specific operation for Quad-SPI nor flash.
29 * It configures specific operation for Quad-SPI nor flash such as lock
35 * NPCX Get specific operation for Quad-SPI nor flash.
37 * It returns current specific operation for Quad-SPI nor flash.
/Zephyr-latest/drivers/memc/
DKconfig.nxp_s325 bool "NXP S32 Quad Serial Peripheral Interface (QSPI) controller"
10 Enable NXP S32 Quad Serial Peripheral Interface (QSPI) controller.
/Zephyr-latest/dts/bindings/mtd/
Dnordic,qspi-nor.yaml31 quad-enable-requirements:
40 - "read4o" # Quad data line SPI, READ4O (0x6B)
41 - "read4io" # Quad data line SPI, READ4IO (0xEB)
51 - "pp4o" # Quad data line SPI, PP4O (0x32)
52 - "pp4io" # Quad data line SPI, PP4IO (0x38)
/Zephyr-latest/drivers/spi/
DKconfig.xlnx7 bool "Xilinx AXI Quad SPI driver"
12 Enable Xilinx AXI Quad SPI v3.2 driver.
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml76 (should be transmitted in quad bus mode).
82 all bytes be sent in quad bus mode. It's a pre-requisite that read and write
172 - "quad-spi"
184 - "quad-spi"
196 - "quad-spi"
208 - "quad-spi"
220 - "quad-spi"
231 - "quad-spi"
243 - "quad-spi"
255 - "quad-spi"
/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-qspi-nor.yaml53 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
54 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
59 There is no info about quad page program opcodes in the SFDP
63 If absent, then 1-4-4 program page is used in quad mode.
Dnuvoton,npcx-fiu-qspi.yaml5 Properties defining the NPCX Quad-SPI peripheral of Flash Interface Unit (FIU).
6 A npcx quad-spi dt node would typically looks like:
Dst,stm32-ospi-nor.yaml47 - OSPI_QUAD_MODE <4> = Quad mode on 4 data lines
71 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
72 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
77 There is no info about quad page program opcodes in the SFDP
/Zephyr-latest/tests/boards/mec15xxevb_assy6853/qspi/src/
Dmain.c355 * @brief Write data into flash using spi quad mode
357 * - check and make sure spi quad mode is enabled
358 * - write data using spi quad mode
365 /* read register2 to judge whether quad mode is enabled */ in test_spi_quad_write()
388 /* set register2 QE=1 to enable quad mode */ in test_spi_quad_write()
429 /* read register2 to confirm quad mode is enabled */ in test_spi_quad_write()
474 /* configure spi quad mode */ in test_spi_quad_write()
479 /* write data using spi quad mode */ in test_spi_quad_write()
480 /* send quad write opcode and address using single mode */ in test_spi_quad_write()
499 zassert_true(ret == 0, "Send quad write data spi_transceive failure: " in test_spi_quad_write()
[all …]
/Zephyr-latest/tests/boards/mec172xevb_assy6906/qspi/src/
Dmain.c87 * SPI clocks based on single, dual, or quad mode.
88 * mode = 1(full-duplex), 2(dual), 4(quad)
91 * quad: 2 clocks per byte
344 * quad one byte is 2 clocks.
470 * @brief Write data into flash using spi quad mode
472 * - check and make sure spi quad mode is enabled
473 * - write data using spi quad mode
484 /* read register2 to judge whether quad mode is enabled */ in test_spi_quad_write()
488 /* set register2 QE=1 to enable quad mode. We write the volatile STATUS2 register in test_spi_quad_write()
501 /* read register2 to confirm quad mode is enabled */ in test_spi_quad_write()
[all …]
/Zephyr-latest/samples/boards/nxp/adsp/number_crunching/
DREADME.rst92 [Library Test] == Bi-quad Real Block IIR test ==
94 [Library Test] Bi-quad Real Block IIR takes 506702 cycles
95 [Library Test] == Bi-quad Real Block IIR end ==
130 [Library Test] == Bi-quad Real Block IIR test ==
132 [Library Test] Bi-quad Real Block IIR takes 13501 cycles
133 [Library Test] == Bi-quad Real Block IIR end ==
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70-qspi.yaml20 qspi-quad-mode:
23 If specified, Use QSPI in quad mode (4 IO lines) otherwise in
/Zephyr-latest/include/zephyr/linker/common-rom/
Dcommon-rom-init.ld24 QUAD((__ZEPHYR_CTOR_END__ - __ZEPHYR_CTOR_LIST__) / 8 - 2)
27 QUAD(0)
29 QUAD(0)
/Zephyr-latest/samples/boards/nxp/adsp/number_crunching/src/
Dcmsis_dsp_wrapper.c54 * Each Bi-quad stage has 4 state variables. in real_block_iir_32()
62 * Initialize the state and coefficient buffers for all Bi-quad sections in real_block_iir_32()
66 /* Call the Q31 Bi-quad Cascade DF1 process function */ in real_block_iir_32()
/Zephyr-latest/dts/bindings/counter/
Dnxp,imx-tmr.yaml4 description: NXP MCUX Quad Timer Channel. Each channel of each quad timer can operate independently
/Zephyr-latest/arch/xtensa/core/
DREADME_WINDOWS.rst15 The first quad (A0-A3) is pointed to by a special register called
51 WINDOWSTART stores a bitmask with one bit per hardware quad (so it's 8
60 So the CPU executing RETW checks to make sure that the register quad
67 register's quad and WINDOWBASE. If there is, the CPU traps to a spill
71 to spill a second quad, and even a third time at maximum.
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h153 /* Continuous mode read: transmit-quad 24-bit address and mode byte */
160 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
175 /* Enter Continuous mode: transmit-single CM quad read opcode */
182 /* Enter Continuous mode: transmit-quad 24-bit address and mode byte */
189 /* Enter Continuous mode: read-quad 3 bytes */
226 /* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */
246 /* Enter Continuous mode: transmit-single CM quad read opcode */
253 /* Enter Continuous mode: transmit-quad 32-bit address and mode byte */
260 /* Enter Continuous mode: read-quad 3 bytes */
/Zephyr-latest/boards/firefly/roc_rk3568_pc/
Dboard.yml3 full_name: ROC-RK3568-PC (Quad-core Cortex-A55)
/Zephyr-latest/drivers/sensor/nxp/qdec_nxp_s32/
DKconfig5 bool "NXP Quad Decoder S32 drivers"

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