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/Zephyr-Core-2.7.6/soc/riscv/riscv-ite/it8xxx2/
Dsoc.c31 * PLL frequency setting = 4 (48MHz)
32 * FND div = 0 (PLL / 1 = 48 mhz)
33 * UART div = 1 (PLL / 2 = 24 mhz)
34 * SMB div = 1 (PLL / 2 = 24 mhz)
35 * SSPI div = 1 (PLL / 2 = 24 mhz)
37 * JTAG div = 1 (PLL / 2 = 24 mhz)
38 * PWM div = 0 (PLL / 1 = 48 mhz)
39 * USBPD div = 5 (PLL / 6 = 8 mhz)
59 void __intc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll) in chip_run_pll_sequence() argument
64 * Configure PLL clock dividers. in chip_run_pll_sequence()
[all …]
/Zephyr-Core-2.7.6/drivers/clock_control/
DKconfig.stm32l4_l5_wb_wl1 # STM32L4, STM32L5, STM32WB and STM32WL PLL configuration options
9 int "PLL divisor"
15 PLL divisor,
16 L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz
17 L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz
18 WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
19 WL: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
22 int "PLL multiplier"
28 PLL multiplier,
29 L4: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
[all …]
DKconfig.stm32g01 # STM32G0 PLL configuration options
9 int "PLL multiplier"
14 PLL multiplier, allowed values: 8-86
15 PLL output must not exceed 56MHz(1.8V)/26MHz(1.2V).
18 int "PLL divisor"
23 PLL divisor, allowed values: 1-8.
26 int "PLL P Divisor"
31 PLL P VCO divisor, allowed values: 2-32.
34 int "PLL Q Divisor"
40 PLL Q VCO divisor, allowed values: 2-8.
[all …]
DKconfig.stm32g41 # STM32G4 PLL configuration options
9 int "PLL divisor"
14 PLL divisor, allowed values: 1-16.
17 int "PLL multiplier"
22 PLL multiplier, allowed values: 8-127.
25 int "PLL P Divisor"
30 PLL P Output divisor, allowed values: 7, 17.
33 int "PLL Q Divisor"
38 PLL Q Output divisor, allowed values: 2, 4, 6, 8.
41 int "PLL R Divisor"
[all …]
DKconfig.stm32f11 # STM32F1 PLL configuration options
9 bool "HSE to PLL /2 prescaler"
12 Enable this option to enable /2 prescaler on HSE to PLL clock signal
15 int "PLL multiplier"
21 PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
31 PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.
DKconfig.stm32l0_l11 # STM32L0 and STM32L1 PLL configuration options
9 int "PLL multiplier"
14 PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48.
15 PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).
18 int "PLL divisor"
23 PLL divisor, allowed values: 2-4.
DKconfig.stm32f0_f31 # STM32F0 and STM32F3 PLL configuration options
14 PREDIV is a PLL clock signal prescaler for the HSE output.
25 PREDIV1 is a PLL clock signal prescaler for any PLL input.
32 int "PLL multiplier"
37 PLL multiplier, allowed values: 2-16.
38 PLL output must not exceed 48MHz for STM32F0 series
DKconfig.stm32h71 # STM32H7 PLL configuration options
65 # PLL settings
68 int "PLL divisor"
73 PLL divisor, allowed values: 0-63.
81 PLL multiplier, allowed values: 4-512.
84 int "PLL P Divisor"
89 PLL P Output divisor, allowed values: 1-128.
92 int "PLL Q Divisor"
97 PLL Q Output divisor, allowed values: 1-128.
100 int "PLL R Divisor"
[all …]
Dclock_stm32f1.c22 * Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and
34 * @brief fill in pll configuration structure
56 /* In case PLL source is HSI, prediv is 2 */ in config_pll_init()
59 /* In case PLL source is not HSI, set prediv case by case */ in config_pll_init()
61 /* PLL prediv */ in config_pll_init()
65 * PLLXPTRE (depends on PLL source HSE) in config_pll_init()
66 * HSE/2 used as PLL source in config_pll_init()
72 * PLLXPTRE (depends on PLL source HSE) in config_pll_init()
73 * HSE used as direct PLL source in config_pll_init()
/Zephyr-Core-2.7.6/dts/bindings/clock/
Dst,stm32wb-pll-clock.yaml5 STM32WB and STM32WL PLL node.
7 It can be used to describe 2 different PLLs: PLL, PLLSAI1.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed:
27 compatible: "st,stm32wb-pll-clock"
42 Main PLL division factor for PLL input clock
49 Main PLL multiplication factor for VCO
56 Main PLL division factor for PLLPCLK
[all …]
Dst,stm32g0-pll-clock.yaml5 PLL node binding for STM32G0 devices
11 PLL can have up to 3 output clocks and for each output clock, the
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 64 MHz.
22 compatible: "st,stm32g0-pll-clock"
37 Division factor for PLL input clock
44 Main PLL multiplication factor for VCO
51 PLL division factor for PLL P output
58 PLL division factor for PLL Q output
65 PLL division factor for PLLCLK (system clock)
Dst,stm32l0-pll-clock.yaml5 STM32L0 and STM32L1 Main PLL node binding:
10 The desired PLL frequency can be computed with the following formula:
12 f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
14 with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16 The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
33 PLL output division
43 PLL multiplication factor for VCO
44 The PLL VCO clock frequency must not exceed:
48 If the USB uses the PLL as clock source, the PLL VCO clock must be
Dst,stm32l4-pll-clock.yaml5 PLL node binding for STM32L4 and STM32L5 devices
7 It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32l4-pll-clock"
40 Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
48 Main PLL multiplication factor for VCO
55 Main PLL division factor for PLLSAI3CLK
[all …]
Dst,stm32f4-pll-clock.yaml5 STM32L4 Main PLL node binding:
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19 The PLL output frequency must not exceed 80 MHz.
22 compatible: "st,stm32f4-pll-clock"
37 Division factor for the PLL input clock
44 Main PLL multiplication factor for VCO
51 Main PLL division factor for PLLSAI2CLK
62 Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
Dst,stm32g4-pll-clock.yaml5 PLL node binding for STM32G4 devices
11 PLL can have up to 3 output clocks and for each output clock, the
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 170 MHz.
22 compatible: "st,stm32g4-pll-clock"
25 - name: st,stm32l4-pll-clock.yaml
36 Division factor for PLL input clock
43 Main PLL multiplication factor for VCO
Dst,stm32f2-pll-clock.yaml5 STM32F2 Main PLL node binding:
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
17 The PLL output frequency must not exceed 168 MHz.
20 compatible: "st,stm32f2-pll-clock"
35 Division factor for the PLL input clock
42 PLL multiplication factor for VCO
49 PLL division factor for PLLCLK
60 PLL division factor for PLL48CK
Dst,stm32h7-pll-clock.yaml5 PLL node binding for STM32H7 devices
7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
14 Each PLL can have up to 3 output clocks and for each output clock, the
23 The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32h7-pll-clock"
48 Main PLL multiplication factor for VCOx
55 PLL division factor for pllx_p_ck
62 PLL division factor for pllx_q_ck
69 PLL division factor for pllx_r_ck
Dst,stm32f7-pll-clock.yaml5 STM32F7 Main PLL node binding:
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
33 Division factor for the PLL input clock
40 PLL multiplication factor for VCO
47 PLL division factor for PLLCLK
58 PLL division factor for PLL48CK
Dst,stm32f1-pll-clock.yaml5 Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
16 The PLL output frequency must not exceed 72 MHz.
19 compatible: "st,stm32f1-pll-clock"
34 Main PLL multiplication factor for VCO
41 Otpional HSE divider for PLL entry
47 Otpional HSE divider for PLL entry
Dst,stm32f100-pll-clock.yaml5 Main PLL node binding for STM32F100 devices
20 The PLL output frequency must not exceed 24 MHz.
23 compatible: "st,stm32f100-pll-clock"
26 - name: st,stm32f105-pll-clock.yaml
35 PLL multiplication factor for output clock
Dst,stm32u5-pll-clock.yaml5 PLL node binding for STM32U5 devices
8 Only main PLL (PLL1) is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
26 The PLL output frequency must not exceed 160 MHz.
28 compatible: "st,stm32u5-pll-clock"
/Zephyr-Core-2.7.6/include/drivers/clock_control/
Dstm32_clock_control.h165 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
166 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
167 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
168 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
169 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
170 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
171 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
172 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
173 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
174 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
[all …]
/Zephyr-Core-2.7.6/soc/arm/arm/beetle/
Dsoc_pll.h8 * @file SoC configuration macros for the ARM LTD Beetle SoC PLL.
16 * This header provides the defines to configure the Beetle PLL.
18 * BEETLE PLL main register is the PLLCTRL in the System Control
25 * The formula to calculate the output frequency of the PLL is:
37 * BEETLE PLL has a non bypassable divider by 2 in output
39 * BEETLE PLL derived clock is prescaled [1-16]
42 /* BEETLE PLL Masks */
47 /* BEETLE PLL Configuration */
50 /* BEETLE PLL Supported Frequencies */
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/same70/
DKconfig.soc94 The main clock is being used to drive the PLL, and
117 int "PLL MULA"
121 This is the multiplier MULA used by the PLL.
127 Setting MULA=0 would disable PLL at boot, this is currently
131 PLL is running at 25 times the main clock frequency.
134 int "PLL DIVA"
138 This is the divider DIVA used by the PLL.
144 Setting DIVA=0 would disable PLL at boot, this is currently
148 PLL is running at 25 times the main clock frequency.
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/samv71/
DKconfig.soc95 The main clock is being used to drive the PLL, and
118 int "PLL MULA"
122 This is the multiplier MULA used by the PLL.
128 Setting MULA=0 would disable PLL at boot, this is currently
132 PLL is running at 25 times the main clock frequency.
135 int "PLL DIVA"
139 This is the divider DIVA used by the PLL.
145 Setting DIVA=0 would disable PLL at boot, this is currently
149 PLL is running at 25 times the main clock frequency.

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