1# Copyright (c) 2021, Linaro ltd 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 Main PLL node binding for STM32F100 devices 6 7 Takes one of clk_hse or clk_hsi as input clock. 8 When clk_hsi is used a fixed prescaler is applied. When input clock is hse or 9 pll2, configurable prescaler is used. 10 11 Up to 2 output clocks could be supported and for each output clock, the 12 frequency can be computed with the following formula: 13 14 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock) 15 16 with, depending on the case: 17 f(PLLIN) = f(input_clk) / 2 if input_clk = clk_hsi 18 f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse 19 20 The PLL output frequency must not exceed 24 MHz. 21 22 23compatible: "st,stm32f100-pll-clock" 24 25include: 26 - name: st,stm32f105-pll-clock.yaml 27 property-blocklist: 28 - mul 29 30properties: 31 mul: 32 type: int 33 required: true 34 description: | 35 PLL multiplication factor for output clock 36 Valid range: 2 - 16 37
