1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
6
7  Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
8  as input clock.
9
10  Up to 2 output clocks could be supported and for each output clock, the
11  frequency can be computed with the following formula:
12
13    f(PLLCLK) = f(input clk) x PLLMUL  --> SYSCLK (System Clock)
14    f(USBCLK) = f(PLLCLK) / USBPRE     --> USB
15
16  The PLL output frequency must not exceed 72 MHz.
17
18
19compatible: "st,stm32f1-pll-clock"
20
21include: [clock-controller.yaml, base.yaml]
22
23properties:
24    "#clock-cells":
25      const: 0
26
27    clocks:
28      required: true
29
30    mul:
31      type: int
32      required: true
33      description: |
34          Main PLL multiplication factor for VCO
35          Valid range: 2 - 16
36
37    xtpre:
38      type: boolean
39      required: false
40      description: |
41          Otpional HSE divider for PLL entry
42
43    usbpre:
44      type: int
45      required: false
46      description: |
47          Otpional HSE divider for PLL entry
48