Searched full:p9 (Results 1 – 24 of 24) sorted by relevance
| /Zephyr-latest/dts/bindings/gpio/ |
| D | nordic-thingy53-edge-connector.yaml | 14 P9 P0.04/AIN0
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| /Zephyr-latest/boards/nordic/nrf54h20dk/doc/ |
| D | index.rst | 112 * LED1 (green) = P9.0
113 * LED2 (green) = P9.1
114 * LED3 (green) = P9.2
115 * LED4 (green) = P9.3
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| /Zephyr-latest/boards/bbc/microbit/ |
| D | board.h | 24 #define EXT_P9_GPIO_PIN 10 /* P9, LED Col 7 */
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| D | bbc_microbit.dts | 92 <9 0 &gpio0 10 0>, /* P9, LED Col 7 */
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| /Zephyr-latest/boards/nordic/thingy53/doc/ |
| D | index.rst | 35 programmer is attached to the P9 programming header.
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| /Zephyr-latest/soc/nordic/nrf54h/bicr/ |
| D | bicr-schema.json | 95 "title": "P9 power supply (VDDIO_P9)",
97 "Not supplied (P9 not used)",
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| D | bicrgen.py | 215 p9_supply=IoPortPowerExtended(ioport_power1.enum_get("P9")),
238 ioport_power1.enum_set("P9", self.p9_supply.value)
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ifx_cat1-pinctrl.h | 83 #define P9 CYHAL_PORT_9 macro
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| /Zephyr-latest/drivers/sensor/bosch/bmp388/ |
| D | bmp388.c | 351 partial_data3 = partial_data2 + (65536 * cal->p9); in bmp388_compensate_press()
427 cal->p9 = (int16_t)sys_le16_to_cpu(cal->p9); in bmp388_get_calibration_data()
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| D | bmp388.h | 166 int16_t p9; member
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| /Zephyr-latest/boards/nordic/thingy53/ |
| D | thingy53_nrf5340_cpunet.dts | 78 <9 0 &gpio0 4 0>, /* P9, P0.04/AIN0 */
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| D | thingy53_nrf5340_common.dtsi | 72 <9 0 &gpio0 4 0>, /* P9, P0.04/AIN0 */
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| /Zephyr-latest/boards/beagle/beaglev_fire/doc/ |
| D | index.rst | 9 RISC-V architecture and FPGA technology. It has the same P8 & P9 cape header pins as BeagleBone
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| /Zephyr-latest/boards/bbc/microbit_v2/ |
| D | bbc_microbit_v2.dts | 91 <9 0 &gpio0 9 0>, /* P9 */
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| /Zephyr-latest/boards/nordic/nrf54h20dk/ |
| D | nrf54h20dk_nrf54h20_cpuapp.dts | 102 * configuration to pass PWM signal on pis 0 and 1. First valid config is P9.2.
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| /Zephyr-latest/boards/nordic/nrf9280pdk/ |
| D | nrf9280pdk_nrf9280_cpuapp.dts | 104 * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2.
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| /Zephyr-latest/boards/adi/eval_adin2111ebz/doc/ |
| D | index.rst | 117 Same UART1 TX and RX cmos signals are available before the FT232, at P9 connector.
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| /Zephyr-latest/boards/adi/apard32690/doc/ |
| D | index.rst | 189 SWD port. SWD debug can be accessed through the Cortex 10-pin connector, P9.
200 be connected to the standard 2*5 pin debug connector (P9) using an
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| /Zephyr-latest/boards/cypress/cy8ckit_062_ble/doc/ |
| D | index.rst | 275 The P9 pins are available at J2. Those signals should be routed to J6.
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| /Zephyr-latest/boards/nxp/mr_canhubk3/doc/ |
| D | index.rst | 272 The 100Base-T1 signals are available in connector ``P9`` and can be converted to
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| /Zephyr-latest/boards/madmachine/mm_feather/doc/ |
| D | index.rst | 105 | P9 | GPIO_AD_B1_03 | D9 | GPIO1_IO19 | | |
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| /Zephyr-latest/boards/nordic/thingy52/doc/ |
| D | index.rst | 355 programmer is attached to the P9 programming header.
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| /Zephyr-latest/boards/madmachine/mm_swiftio/doc/ |
| D | index.rst | 85 | P9 | GPIO_B0_00 | D9 | GPIO2_IO00 | | |
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| /Zephyr-latest/boards/nordic/nrf52dk/doc/ |
| D | index.rst | 281 P3/P9 Digital I/O
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