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/Zephyr-latest/soc/silabs/silabs_sim3/sim3u/
Dgen_crossbar_config.py23 have multiple bits to prevent having to mux unused pins (like UART flow control).
31 A crossbar has a list of signals that it tries to mux to pins that it controls. That list has a
165 def mux(self, muxs): member in Crossbar
169 for mux in muxs:
170 if self.number == 0 and mux.pin[0] != 0 and mux.pin[0] != 1:
172 if self.number == 1 and mux.pin[0] != 2 and mux.pin[0] != 3:
175 if mux.signal not in bit.signals:
177 if mux.signal in signal_muxs:
178 raise Exception("duplicate signal", mux)
179 if mux.pin < bit.pin_first or mux.pin > bit.pin_last:
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_rv32m1.c24 #define PIN(mux) (((mux) & 0xFC00000) >> 22) argument
25 #define PORT(mux) (((mux) & 0xF0000000) >> 28) argument
26 #define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK) argument
38 uint16_t mux = PINCFG(pins[i]); in pinctrl_configure_pins() local
40 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux; in pinctrl_configure_pins()
Dpinctrl_nxp_port.c33 #define PIN(mux) (((mux) & 0xFC00000) >> 22) argument
34 #define PORT(mux) (((mux) & 0xF0000000) >> 28) argument
35 #define PINCFG(mux) ((mux) & Z_PINCTRL_NXP_PORT_PCR_MASK) argument
48 uint16_t mux = PINCFG(pins[i]); in pinctrl_configure_pins() local
50 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux; in pinctrl_configure_pins()
Dpinctrl_lpc_iocon.c14 #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) argument
15 #define TYPE(mux) (((mux) & 0xC0000) >> 18) argument
Dpinctrl_stm32.c226 uint32_t pin, mux; in pinctrl_configure_pins() local
240 mux = pins[i].pinmux; in pinctrl_configure_pins()
245 if (STM32_DT_PINMUX_FUNC(mux) == ALTERNATE) { in pinctrl_configure_pins()
247 } else if (STM32_DT_PINMUX_FUNC(mux) == ANALOG) { in pinctrl_configure_pins()
249 } else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_IN) { in pinctrl_configure_pins()
257 } else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_OUT) { in pinctrl_configure_pins()
261 __ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux)); in pinctrl_configure_pins()
264 if (STM32_DT_PINMUX_FUNC(mux) < STM32_ANALOG) { in pinctrl_configure_pins()
266 } else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) { in pinctrl_configure_pins()
268 } else if (STM32_DT_PINMUX_FUNC(mux) == STM32_GPIO) { in pinctrl_configure_pins()
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dsoc.c104 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; in clock_init()
110 rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; in clock_init()
182 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; in clock_init()
189 rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; in clock_init()
195 rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; in clock_init()
200 rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; in clock_init()
205 rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; in clock_init()
210 rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; in clock_init()
216 rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; in clock_init()
223 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut; in clock_init()
[all …]
/Zephyr-latest/dts/bindings/test/
Dvnd,i2c-mux.yaml5 I2C mux
11 compatible: "vnd,i2c-mux"
16 description: I2C mux controller
17 compatible: "vnd,i2c-mux-controller"
/Zephyr-latest/boards/nxp/imx93_evk/dts/bindings/
Dimx93evk-exp-sel.yaml14 mux-gpios:
17 description: Pin used to select the MUX
19 mux:
25 description: MUX choice
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx-iomuxc-scu.yaml13 description: SCFW-based IOMUXC pin mux.
19 This is an array of values defining the pin mux selection
22 <pad, mux>
25 mux: Select which signal to route.
Dnxp,mci-io-mux.yaml5 MCI IO MUX pin control node. This node defines pin configurations in pin
33 compatible: "nxp,mci-io-mux"
39 description: MCI IO MUX pin controller pin group
42 MCI IO MUX pin controller pin configuration node
53 Pin mux selection for this group. See the SOC level pinctrl header
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Drv32m1-pinctrl.h11 * @brief Specify PORTx->PCR register MUX field
15 * @param mux Alternate function number (0 to 7)
17 #define RV32M1_MUX(port, pin, mux) \ argument
20 (((mux) & 0x7) << 8))
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.c235 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; in clock_init()
239 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; in clock_init()
245 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; in clock_init()
249 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; in clock_init()
314 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; in clock_init()
321 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; in clock_init()
326 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; in clock_init()
333 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; in clock_init()
338 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3; in clock_init()
345 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; in clock_init()
[all …]
/Zephyr-latest/boards/nxp/imx93_evk/
Dboard.c24 const struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(BOARD_EXP_SEL_NODE, mux_gpios); in board_init_exp_sel() local
25 uint32_t pin_state = DT_ENUM_IDX(BOARD_EXP_SEL_NODE, mux); in board_init_exp_sel()
27 if (!gpio_is_ready_dt(&mux)) { in board_init_exp_sel()
39 rc = gpio_pin_configure_dt(&mux, pin_state); in board_init_exp_sel()
44 LOG_INF("EXP_SEL mux %c with priority %d", pin_state ? 'B' : 'A', in board_init_exp_sel()
DKconfig7 bool "Configure i.MX 93 EVK board mux control during init"
11 int "i.MX 93 EVK board mux control init priority"
DKconfig.defconfig10 # Enable board mux configure during init
14 # CAN Phy must be initialized after board mux
/Zephyr-latest/dts/bindings/dma/
Dnxp,edma.yaml29 # IMPORTANT: if your EDMA version doesn't support channel MUX-ing please
30 # leave the MUX cell as 0. This is not mandatory for the driver as the
31 # MUX value will be ignored in this case but all entities using EDMA should
35 - mux
/Zephyr-latest/tests/drivers/build_all/comparator/mcux_acmp/
Dmke15z7_mux_dac.dts14 positive-mux-input = "IN0";
15 positive-port-input = "MUX";
16 negative-mux-input = "IN0";
Dmimxrt1176_mux_dac.dts23 positive-mux-input = "IN2";
24 positive-port-input = "MUX";
25 negative-mux-input = "IN2";
Dmke15z7_mux_mux.dts14 positive-mux-input = "IN0";
15 negative-mux-input = "IN1";
Dmimxrt1176_mux_mux.dts24 positive-mux-input = "IN1";
25 negative-mux-input = "IN2";
/Zephyr-latest/boards/digilent/arty_a7/
Dboard.c22 struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(DAPLINK_QSPI_MUX_NODE, mux_gpios); in board_daplink_qspi_mux_select() local
38 if (!gpio_is_ready_dt(&mux)) { in board_daplink_qspi_mux_select()
39 LOG_ERR("DAPLink QSPI MUX GPIO device not ready"); in board_daplink_qspi_mux_select()
43 err = gpio_pin_configure_dt(&mux, flags); in board_daplink_qspi_mux_select()
45 LOG_ERR("failed to configure DAPLink QSPI MUX GPIO (err %d)", in board_daplink_qspi_mux_select()
/Zephyr-latest/soc/nxp/rw/
Dpinctrl_defs.h25 #define IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(mux) ((mux) & 0x1) argument
26 #define IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(mux) (((mux) >> 1) & 0x7) argument
27 #define IOMUX_GET_SCTIMER_IN_CLR_ENABLE(mux) (((mux) >> 4) & 0x1) argument
28 #define IOMUX_GET_SCTIMER_IN_CLR_OFFSET(mux) (((mux) >> 5) & 0x7) argument
29 #define IOMUX_GET_CTIMER_CLR_ENABLE(mux) (((mux) >> 8) & 0x1ULL) argument
30 #define IOMUX_GET_CTIMER_CLR_OFFSET(mux) (((mux) >> 9) & 0xFULL) argument
31 #define IOMUX_GET_FSEL_CLR_MASK(mux) (((mux) >> 13) & 0xFFFFFFFFULL) argument
32 #define IOMUX_GET_FLEXCOMM_CLR_MASK(mux) \ argument
33 (((mux) >> 45) & 0x7FFULL)
34 #define IOMUX_GET_FLEXCOMM_CLR_IDX(mux) \ argument
[all …]
/Zephyr-latest/tests/drivers/comparator/gpio_loopback/boards/
Dfrdm_ke15z.overlay42 positive-mux-input = "IN0";
43 positive-port-input = "MUX";
44 negative-mux-input = "IN0";
/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
116 positive-mux-input:
128 negative-mux-input:
144 - MUX
150 - MUX
/Zephyr-latest/boards/digilent/arty_a7/dts/bindings/
Darm,daplink-qspi-mux.yaml6 compatible: "arm,daplink-qspi-mux"
17 mux-gpios:

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