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/Zephyr-Core-3.5.0/dts/bindings/i2s/
Dst,stm32-i2s.yaml29 mck-enabled:
33 An mck pin must be listed within pinctrl-0 when enabling this property.
Dnordic,nrf-i2s.yaml25 (MCK) generator. The generator is only needed when the I2S peripheral
/Zephyr-Core-3.5.0/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
35 and OE inputs respectively. Assuming that MCK is 120MHz (cpu at full speed)
36 each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
123 where each value is configured in terms of MCK cycles. The SMC
135 each value is configured in terms of MCK cycles and a value of 0 is forbidden.
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
DKconfig.soc26 and main 96 MHz clock (MCK):
27 HCLK = MCK / PROC_CLK_DIV
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
DKconfig.soc25 and master clock (MCK):
26 HCLK = MCK / PROC_CLK_DIV
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/same70/
Dsoc.c155 /* Switch MCK (Master Clock) to the main clock first */ in clock_init()
208 /* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */ in clock_init()
242 * (MCK) frequency. in z_arm_platform_init()
243 * TODO: set FWS based on the actual MCK frequency and VDDIO value in z_arm_platform_init()
DKconfig.soc113 and master clock (MCK):
114 MCK = HCLK / MDIV
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/samv71/
Dsoc.c155 /* Switch MCK (Master Clock) to the main clock first */ in clock_init()
208 /* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */ in clock_init()
242 * (MCK) frequency. in z_arm_platform_init()
243 * TODO: set FWS based on the actual MCK frequency and VDDIO value in z_arm_platform_init()
DKconfig.soc114 and master clock (MCK):
115 MCK = HCLK / MDIV
/Zephyr-Core-3.5.0/dts/bindings/dac/
Datmel,sam-dac.yaml24 PRESCAL = (MCK / DACClock) - 2. Should be in range from 0 to 15. The
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam3x/
Dsoc.c140 /* Switch MCK (Master Clock) to the main clock first */ in clock_init()
199 * (MCK) frequency. in z_arm_platform_init()
200 * TODO: set FWS based on the actual MCK frequency and VDDCORE value in z_arm_platform_init()
Dsoc.h46 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/same54/
Dsoc.h42 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/same51/
Dsoc.h43 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/same53/
Dsoc.h44 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/samr34/
Dsoc.h36 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/samr35/
Dsoc.h36 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4e/
Dsoc.h46 /** Master Clock (MCK) Frequency */
Dsoc.c127 /* Switch MCK (Master Clock) to the main clock first. */ in clock_init()
186 * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet. in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/samd51/
Dsoc.h51 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4s/
Dsoc.h60 /** Master Clock (MCK) Frequency */
Dsoc.c127 /* Switch MCK (Master Clock) to the main clock first. */ in clock_init()
186 * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/samc21/
Dsoc.h66 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/samc20/
Dsoc.h66 /** Master Clock (MCK) Frequency */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/saml21/
Dsoc.h52 /** Master Clock (MCK) Frequency */

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