1 /* Copyright (c) 2021 Argentum Systems Ltd. 2 * 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef _ATMEL_SAML_SOC_H_ 7 #define _ATMEL_SAML_SOC_H_ 8 9 #ifndef _ASMLANGUAGE 10 11 #define DONT_USE_CMSIS_INIT 12 13 #if defined(CONFIG_SOC_PART_NUMBER_SAML21E15B) 14 #include <saml21e15b.h> 15 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21E16B) 16 #include <saml21e16b.h> 17 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21E17B) 18 #include <saml21e17b.h> 19 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21E18B) 20 #include <saml21e18b.h> 21 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21G16B) 22 #include <saml21g16b.h> 23 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21G17B) 24 #include <saml21g17b.h> 25 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21G18B) 26 #include <saml21g18b.h> 27 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21J16B) 28 #include <saml21j16b.h> 29 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17B) 30 #include <saml21j17b.h> 31 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17BU) 32 #include <saml21j17bu.h> 33 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18B) 34 #include <saml21j18b.h> 35 #elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18BU) 36 #include <saml21j18bu.h> 37 #else 38 #error Library does not support the specified device. 39 #endif 40 41 #endif /* _ASMLANGUAGE */ 42 43 #define ADC_SAM0_REFERENCE_ENABLE_PROTECTED 44 45 #include "adc_fixup_sam0.h" 46 #include "../common/soc_port.h" 47 #include "../common/atmel_sam0_dt.h" 48 49 /** Processor Clock (HCLK) Frequency */ 50 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 51 52 /** Master Clock (MCK) Frequency */ 53 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 54 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 55 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 56 #define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 57 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 58 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 59 60 #if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) 61 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 62 #elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) 63 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 64 #elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) 65 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 66 #elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) 67 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 68 #else 69 #error Unsupported GCLK1 clock source. 70 #endif 71 72 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 73 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 74 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 75 76 #endif /* _ATMEL_SAML_SOC_H_ */ 77
