1 /* Copyright (c) 2021 Argentum Systems Ltd. 2 * 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef _ATMEL_SAMR_SOC_H_ 7 #define _ATMEL_SAMR_SOC_H_ 8 9 #ifndef _ASMLANGUAGE 10 11 #define DONT_USE_CMSIS_INIT 12 13 #include <zephyr/types.h> 14 15 #if defined(CONFIG_SOC_PART_NUMBER_SAMR34J16B) 16 #include <samr34j16b.h> 17 #elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J17B) 18 #include <samr34j17b.h> 19 #elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J18B) 20 #include <samr34j18b.h> 21 #else 22 #error Library does not support the specified device. 23 #endif 24 25 #endif /* _ASMLANGUAGE */ 26 27 #define ADC_SAM0_REFERENCE_ENABLE_PROTECTED 28 29 #include "adc_fixup_sam0.h" 30 #include "../common/soc_port.h" 31 #include "../common/atmel_sam0_dt.h" 32 33 /** Processor Clock (HCLK) Frequency */ 34 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 35 36 /** Master Clock (MCK) Frequency */ 37 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 38 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 39 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 40 #define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 41 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 42 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 43 44 #if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) 45 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 46 #elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) 47 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 48 #elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) 49 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 50 #elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) 51 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 52 #else 53 #error Unsupported GCLK1 clock source. 54 #endif 55 56 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 57 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 58 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 59 60 #endif /* _ATMEL_SAMR_SOC_H_ */ 61
