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/Zephyr-latest/dts/bindings/mbox/
Dnxp,mbox-mailbox.yaml4 This NXP Mailbox driver implements Multi-Channel Inter-Processor Mailbox (MBOX) API
5 around NXP Inter-CPU Mailbox peripheral IP block.
7 The NXP Inter-CPU Mailbox provides up to thirty-two user defined interrupts.
12 compatible: "nxp,mbox-mailbox"
14 include: [base.yaml, mailbox-controller.yaml]
20 rx-channels:
25 Setting this value to N, will enable channels 0 to N-1, consecutively.
29 set rx-channels of mailbox as follows:
32 rx-channels = <4>;
36 mbox-cells:
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Dnordic,nrf-vevif-task-rx.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic VEVIF (VPR Event Interface) - TASK RX MODE
10 VEVIF provides support for inter-domain software signaling. It implements a set of tasks
16 cpuppr: cpu@d {
19 compatible = "nordic,nrf-vevif-task-rx";
24 #mbox-cells = <1>;
26 nordic,tasks-mask = <0xfffffff0>;
30 compatible: "nordic,nrf-vevif-task-rx"
32 include: [base.yaml, mailbox-controller.yaml]
40 nordic,tasks-mask:
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/Zephyr-latest/arch/arc/core/
Darc_connect.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/arch/cpu.h>
20 /* Generate an inter-core interrupt to the target core */
28 /* Acknowledge the inter-core interrupt raised by core */
36 /* Read inter-core interrupt status */
49 /* Check the source of inter-core interrupt */
62 /* Clear the inter-core interrupt */
65 uint32_t cpu, c; in z_arc_connect_ici_clear() local
70 cpu = z_arc_connect_cmd_readback(); /* 1,2,4,8... */ in z_arc_connect_ici_clear()
73 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpu can be in z_arc_connect_ici_clear()
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Dsmp.c4 * SPDX-License-Identifier: Apache-2.0
38 * _curr_cpu is used to record the struct of _cpu_t of each cpu.
53 * only one slave cpu can read it per time in arch_cpu_start()
59 /* wait slave cpu to start */ in arch_cpu_start()
104 /* configure inter-core debug unit if available */ in arch_secondary_cpu_init()
171 /* configure inter-core debug unit if available */ in arch_smp_init()
185 "ARC connect has no inter-core interrupt\n"); in arch_smp_init()
186 return -ENODEV; in arch_smp_init()
194 z_arc_connect_gfrc_core_set((1 << arch_num_cpus()) - 1); in arch_smp_init()
199 return -ENODEV; in arch_smp_init()
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/lll/
Dlll_vendor.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
13 * resolutions that consume CPU time between radio events.
14 * Value include max end, start and scheduling CPU usage times.
42 /* Worst-case time margin needed after event end-time in the air
43 * (done/preempt race margin + power-down/chain delay)
50 /* Inter-Event Space (IES) */
65 /* Turnaround time between RX and TX is based on CPU execution speed. It also
67 * imposed by BT Core spec for inter frame spacing (IFS). To include CPUs with
73 /* Sub-microsecond conversion macros. With current timer resolution of ~30 us
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/Zephyr-latest/doc/hardware/peripherals/
Dmbox.rst3 Multi-Channel Inter-Processor Mailbox (MBOX)
11 is providing one or more channels, each one targeting one other CPU cluster
/Zephyr-latest/samples/drivers/ipm/ipm_mhu_dual_core/
DREADME.rst1 .. zephyr:code-sample:: ipm-mhu-dual-core
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) using an MHU (Message Handling Unit)
10 the processor cores. This sample is a simple dual-core example for a
14 1. CPU 0 will wake up CPU 1 after initialization
15 2. CPU 1 will send to CPU 0 an interrupt over MHU0
16 3. CPU 0 return the same to CPU 1 when received MHU0 interrupt
17 4. Test done when CPU 1 received MHU0 interrupt
23 -----------
26 It can be built and executed on Musca B1 CPU 0 as follows:
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/Zephyr-latest/drivers/console/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
5 # SPDX-License-Identifier: Apache-2.0
95 Useful in board bring-up if there aren't any working serial
99 DT_CHOSEN_Z_RAM_CONSOLE := zephyr,ram-console
107 be examined at runtime with a debugger. Useful in board bring-up
117 examined by a debugger or software tool from a parallel-running OS.
126 NULL-terminated leave one byte unused, the actual length is
136 Segger J-Link software and displayed on a computer in real-time.
137 Requires support for Segger J-Link on the companion IC onboard.
153 periodically. Period starts from 1-2 milliseconds and can be increased
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/Zephyr-latest/samples/drivers/ipm/ipm_esp32/
DREADME.rst1 .. zephyr:code-sample:: ipm-esp32
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) between ESP32 APP and PRO CPUs.
12 ESP32 has two CPU named APP and PRO, in this simple example PRO send a
27 .. zephyr-app-commands::
28 :zephyr-app: samples/drivers/ipm/ipm_esp32
30 :west-args: --sysbuild
40 .. code-block:: console
42 *** Booting Zephyr OS build v4.0.0-rc2-61-ga24efebe15e2 ***
/Zephyr-latest/doc/services/ipc/ipc_service/backends/
Dipc_service_icmsg.rst6 The inter core messaging backend (ICMsg) is a lighter alternative to the
27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
28 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
30 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
35 domain (or CPU) that data has been written. Ensure that the other domain
36 (or CPU) is able to receive the signal.
40 Make sure that you set correct value of the ``dcache-alignment``.
46 .. code-block:: devicetree
48 reserved-memory {
60 compatible = "zephyr,ipc-icmsg";
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/Zephyr-latest/boards/qemu/nios2/doc/
Dindex.rst8 This configuration provides support for an Altera Nios-II CPU and these devices:
25 +--------------+------------+----------------------+
28 | IIC | on-chip | Internal interrupt |
30 +--------------+------------+----------------------+
31 | NS16550 | on-chip | serial port |
33 +--------------+------------+----------------------+
34 | TIMER | on-chip | system clock |
35 +--------------+------------+----------------------+
42 ------------
47 -----------
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/Zephyr-latest/boards/croxel/croxel_cx1825/doc/
Dindex.rst7 Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
13 * :abbr:`I2C (Inter-Integrated Circuit)`
27 - Ezurio's BL654 (nRF52840 ARM Cortex-M4F processor at 64MHz)
28 - 1 MB flash memory and 256 KB of SRAM
29 - Coin-cell retainer for Lithium coincell batteries
30 - 2 Discrete LEDs (Red and Green)
31 - User Button
32 - Reset Button
33 - Accelerometer (LIS3DH)
34 - Ambient & RGB Light and Proximity Sensor (APDS9960)
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/Zephyr-latest/doc/introduction/
Dindex.rst6 The Zephyr OS is based on a small-footprint kernel designed for use on
7 resource-constrained and embedded systems: from simple embedded environmental
13 - ARCv2 (EM and HS) and ARCv3 (HS6X)
14 - ARMv6-M, ARMv7-M, and ARMv8-M (Cortex-M)
15 - ARMv7-A and ARMv8-A (Cortex-A, 32- and 64-bit)
16 - ARMv7-R, ARMv8-R (Cortex-R, 32- and 64-bit)
17 - Intel x86 (32- and 64-bit)
18 - MIPS (MIPS32 Release 1 specification)
19 - NIOS II Gen 2
20 - RISC-V (32- and 64-bit)
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/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/
DREADME.rst1 .. zephyr:code-sample:: eth-ivshmem
2 :name: Inter-VM Shared Memory (ivshmem) Ethernet
3 :relevant-api: ivshmem ethernet
20 .. code-block:: console
22 git clone https://github.com/siemens/jailhouse-images.git
23 cd jailhouse-images
29 .. code-block:: console
31 ./kas-container menu
33 Edit "start-qemu.sh":
34 * change ``-cpu cortex-a57`` -> ``-cpu cortex-a53``
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/Zephyr-latest/arch/x86/include/
Dx86_mmu.h2 * Copyright (c) 2011-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017-2020 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
8 * None of these are application-facing, use only if you know what you are
38 #define MMU_RW BITL(1) /** Read-Write */
39 #define MMU_US BITL(2) /** User-Supervisor */
53 /* Unused PTE bits ignored by the CPU, which we use for our own OS purposes.
61 #define PF_P BIT(0) /* 0 Non-present page 1 Protection violation */
66 #define PF_PK BIT(5) /* 1 protection-key violation */
67 #define PF_SGX BIT(15) /* 1 SGX-specific access control requirements */
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/Zephyr-latest/samples/drivers/virtualization/ivshmem/doorbell/
DREADME.rst1 .. zephyr:code-sample:: ivshmem-doorbell
3 :relevant-api: ivshmem
5 Use Inter-VM Shared Memory to exchange messages between two processes running on different
20 ivshmem-server needs to be available and running. The server is available in
21 Zephyr SDK or pre-built in some distributions. Otherwise, it is available in
24 ivshmem-client needs to be available as it is employed in this sample as an
25 external application. The same conditions of ivshmem-server applies to the
26 ivshmem-server, as it is also available via QEMU.
31 Building ivshmem-doorbell is as follows:
36 .. zephyr-app-commands::
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/Zephyr-latest/boards/actinius/icarus_som/doc/
Dindex.rst6 The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module
8 LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for
12 ARM Cortex-M33F CPU, ARMv8-M Security Extension and the
19 * :abbr:`I2C (Inter-Integrated Circuit)`
26 * :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)`
30 .. figure:: img/icarus-som-external-pins.jpg
36 .. figure:: img/icarus-som-peripherals-pins.jpg
45 The detailed information about the on-board hardware can be found at the `Icarus SoM Product Websit…
53 +-----------+------------+----------------------+
56 | ADC | on-chip | adc |
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/Zephyr-latest/boards/actinius/icarus_bee/doc/
Dindex.rst8 LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button,
12 ARM Cortex-M33F CPU, ARMv8-M Security Extension and the
19 * :abbr:`I2C (Inter-Integrated Circuit)`
26 * :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)`
30 .. figure:: img/icarus-bee-external-pins.jpg
36 .. figure:: img/icarus-bee-peripherals-pins.jpg
45 The detailed information about the on-board hardware can be found at the `Icarus Bee Product Websit…
53 +-----------+------------+----------------------+
56 | ADC | on-chip | adc |
57 +-----------+------------+----------------------+
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/Zephyr-latest/boards/adafruit/itsybitsy/doc/
Dindex.rst16 * :abbr:`I2C (Inter-Integrated Circuit)`
17 * :abbr:`I2S (Inter-Integrated Sound)`
25 * :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
31 - nRF52840 ARM Cortex-M4F CPU at 64MHz
32 - 1 MB of flash memory and 256 KB of SRAM
33 - 2 MB of QSPI flash
34 - A user LED
35 - A user switch
36 - An RGB DotStar LED
37 - Native USB port
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/Zephyr-latest/boards/we/ophelia1ev/doc/
Dindex.rst6 The we_ophelia1ev_nrf52805 board is an evaluation board of the Ophelia-I radio module.
7 It provides support for the Nordic Semiconductor nRF52805 ARM CPU and
13 * :abbr:`I2C (Inter-Integrated Circuit)`
19 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
25 The Ophelia-I uses the internal low frequency RC oscillator
36 +-----------+------------+----------------------+
39 | CLOCK | on-chip | clock_control |
40 +-----------+------------+----------------------+
41 | FLASH | on-chip | flash |
42 +-----------+------------+----------------------+
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/Zephyr-latest/boards/u-blox/ubx_evkannab1/doc/
Dindex.rst3 u-blox EVK-ANNA-B11x
9 The u-blox ANNA-B1 Evaluation Kit hardware is a Bluetooth low energy
10 module based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU
17 * :abbr:`I2C (Inter-Integrated Circuit)`
25 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
28 .. figure:: img/EVK-ANNA-B112.jpg
30 EVK ANNA-B1
32 More information about the ANNA-B1 module and the EVK-ANNA-B1
33 can be found at `ANNA-B1 product page`_ and
34 `EVK-ANNA-B1 product page`_.
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/Zephyr-latest/boards/qemu/x86/doc/
Dindex.rst8 This board configuration provides support for an x86 Minute IA (Lakemont) CPU
24 +--------------+------------+-----------------------+
27 | HPET | on-chip | system clock |
28 +--------------+------------+-----------------------+
29 | APIC | on-chip | interrupt controller |
30 +--------------+------------+-----------------------+
31 | NS16550 | on-chip | serial port |
33 +--------------+------------+-----------------------+
39 -------------------------
44 -----------
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/Zephyr-latest/boards/u-blox/ubx_evkninab1/doc/
Dindex.rst3 u-blox EVK NINA-B11x
9 The u-blox NINA-B1 Evaluation Kit hardware is a Bluetooth
11 ARM Cortex-M4F CPU and has support for the following features:
17 * :abbr:`I2C (Inter-Integrated Circuit)`
25 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
28 .. figure:: img/EVK-NINA-B1.jpg
30 EVK NINA-B1
32 More information about the NINA-B1 module and the EVK NINA-B1
33 can be found at `NINA-B1 product page`_ and
34 `EVK-NINA-B1 product page`_.
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/Zephyr-latest/boards/nordic/nrf51dongle/doc/
Dindex.rst10 Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices:
16 * :abbr:`I2C (Inter-Integrated Circuit)`
22 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
49 +-----------+------------+----------------------+
52 | ADC | on-chip | adc |
53 +-----------+------------+----------------------+
54 | CLOCK | on-chip | clock_control |
55 +-----------+------------+----------------------+
56 | FLASH | on-chip | flash |
57 +-----------+------------+----------------------+
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/Zephyr-latest/boards/contextualelectronics/abc/doc/
Dindex.rst7 Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
12 * :abbr:`I2C (Inter-Integrated Circuit)`
18 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
31 - nRF52840 ARM Cortex-M4F processor at 64 MHz
32 - 1 MB flash memory and 256 KB of SRAM
33 - SWD connector
41 +-----------+------------+----------------------+
44 | CLOCK | on-chip | clock_control |
45 +-----------+------------+----------------------+
46 | FLASH | on-chip | flash |
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