Lines Matching +full:inter +full:- +full:cpu

2  * Copyright (c) 2011-2014 Wind River Systems, Inc.
3  * Copyright (c) 2017-2020 Intel Corporation
5  * SPDX-License-Identifier: Apache-2.0
8  * None of these are application-facing, use only if you know what you are
38 #define MMU_RW		BITL(1)		/** Read-Write */
39 #define MMU_US		BITL(2)		/** User-Supervisor */
53 /* Unused PTE bits ignored by the CPU, which we use for our own OS purposes.
61 #define PF_P		BIT(0)	/* 0 Non-present page  1 Protection violation */
66 #define PF_PK		BIT(5)  /* 1 protection-key violation */
67 #define PF_SGX		BIT(15) /* 1 SGX-specific access control requirements */
103  *   . - not present
104  *   w - present, writable, not executable
105  *   a - present, writable, executable
106  *   r - present, read-only, not executable
107  *   x - present, read-only, executable
113  *   yellow - Identity mapping (virt = phys)
114  *    green - Fixed virtual memory mapping (virt = phys + constant)
115  *  magenta - entry is child page table
116  *     cyan - General mapped memory
118  * @param ptables Top-level pointer to the page tables, as programmed in CR3
124 /* Legacy function - set identity-mapped MMU stack guard page to RO in the
153 /* Set CR3 to a physical address. There must be a valid top-level paging  in z_x86_kpti_is_access_ok()
154  * structure here or the CPU will triple fault. The incoming page tables must  in z_x86_kpti_is_access_ok()
182 /* Return the virtual address of the page tables installed in this CPU in CR3 */
213 	    (thread->base.user_options & K_USER) != 0U) {  in z_x86_thread_page_tables_get()
218 		return k_mem_virt_addr(thread->arch.ptables);  in z_x86_thread_page_tables_get()
227 /* Handling function for TLB shootdown inter-processor interrupts. */
235 /* Early-boot paging setup tasks, called from prep_c */