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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dsam0_eic.h4 * SPDX-License-Identifier: Apache-2.0
33 * @brief Acquire an EIC interrupt for specific port and pin combination
35 * This acquires the EIC interrupt for a specific port and pin combination,
41 * @param pin pin in the port
47 int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
51 * @brief Release the EIC interrupt for a specific port and pin combination
53 * Release the EIC configuration for a specific port and pin combination.
58 * @param pin pin in the port
60 int sam0_eic_release(int port, int pin);
63 * @brief Enable the EIC interrupt for a specific port and pin combination
[all …]
Dintc_xmc4xxx.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Enable interrupt for specific port_id and pin combination
14 * @param pin pin Pin the port
21 * @retval -ENOTSUP If the specific port_id/pin combination is not supported or
23 * @retval -EBUSY If the interrupt line is already used by a different port_id/pin
24 * @retval -EINVAL If the trigger combination is invalid
28 int intc_xmc4xxx_gpio_enable_interrupt(int port_id, int pin, enum gpio_int_mode mode,
29 enum gpio_int_trig trig, void(*fn)(const struct device*, int), void *user_data);
32 * @brief Disable interrupt for specific port_id and pin combination
35 * @param pin pin Pin the port
[all …]
/Zephyr-latest/dts/bindings/sdhc/
Despressif,esp32-sdhc-slot.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,esp32-sdhc-slot"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 bus-width:
21 type: int
23 - 1
24 - 4
28 clk-pin:
[all …]
/Zephyr-latest/include/zephyr/drivers/misc/timeaware_gpio/
Dtimeaware_gpio.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for Time-aware GPIO drivers
15 * @brief Time-aware GPIO Interface
16 * @defgroup tgpio_interface Time-aware GPIO Interface
53 int (*pin_disable)(const struct device *dev, uint32_t pin);
54 int (*get_time)(const struct device *dev, uint64_t *current_time);
55 int (*cyc_per_sec)(const struct device *dev, uint32_t *cycles);
56 int (*set_perout)(const struct device *dev, uint32_t pin, uint64_t start_time,
58 int (*config_ext_ts)(const struct device *dev, uint32_t pin, uint32_t event_polarity);
59 int (*read_ts_ec)(const struct device *dev, uint32_t pin, uint64_t *timestamp,
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/src/
Dtest_pin.c4 * SPDX-License-Identifier: Apache-2.0
13 unsigned int pin, in pin_get_raw_and_verify() argument
14 int val_expected, int idx) in pin_get_raw_and_verify()
16 int val_actual; in pin_get_raw_and_verify()
18 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
20 "Test point %d: failed to get physical pin value", idx); in pin_get_raw_and_verify()
22 "Test point %d: invalid physical pin get value", idx); in pin_get_raw_and_verify()
25 static void pin_get_and_verify(const struct device *port, unsigned int pin, in pin_get_and_verify() argument
26 int val_expected, int idx) in pin_get_and_verify()
28 int val_actual; in pin_get_and_verify()
[all …]
Dtest_pin_interrupt.c4 * SPDX-License-Identifier: Apache-2.0
13 static int cb_count;
14 static int cb_count_target;
20 "Detected interrupt on an invalid pin"); in callback_edge()
28 int ret; in callback_level()
31 "Detected interrupt on an invalid pin"); in callback_level()
37 "Failed to disable pin interrupt in the callback"); in callback_level()
41 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
42 int val, in pin_set_and_verify()
43 int idx) in pin_set_and_verify()
[all …]
Dtest_config.c4 * SPDX-License-Identifier: Apache-2.0
16 unsigned int pin, in pin_get_raw_and_verify() argument
17 int val_expected, int idx) in pin_get_raw_and_verify()
19 int val_actual; in pin_get_raw_and_verify()
21 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
23 "Test point %d: failed to get pin value", idx); in pin_get_raw_and_verify()
25 "Test point %d: invalid pin get value", idx); in pin_get_raw_and_verify()
29 unsigned int pin, in pin_set_raw_and_verify() argument
30 int val, int idx) in pin_set_raw_and_verify()
32 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Dnxp,mipi-dbi-flexio-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mipi-dbi-flexio-lcdif"
8 include: [mipi-dbi-controller.yaml, base.yaml, pinctrl-device.yaml]
11 shifters-count:
12 type: int
17 timers-count:
18 type: int
23 enwr-pin:
24 type: int
27 Pin select for WR(8080 mode), EN(6800 mode).
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_sifive.c2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
26 /* sifive GPIO register-set structure */
28 unsigned int in_val;
29 unsigned int in_en;
30 unsigned int out_en;
31 unsigned int out_val;
32 unsigned int pue;
33 unsigned int ds;
34 unsigned int rise_ie;
[all …]
Dgpio_rt1718s_port.c4 * SPDX-License-Identifier: Apache-2.0
39 static int gpio_rt1718s_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in gpio_rt1718s_pin_config() argument
41 const struct gpio_rt1718s_port_config *const config = dev->config; in gpio_rt1718s_pin_config()
42 struct gpio_rt1718s_port_data *const data = dev->data; in gpio_rt1718s_pin_config()
44 int ret = 0; in gpio_rt1718s_pin_config()
48 return -ENOTSUP; in gpio_rt1718s_pin_config()
53 return -ENOTSUP; in gpio_rt1718s_pin_config()
57 if (pin >= RT1718S_GPIO_NUM) { in gpio_rt1718s_pin_config()
58 return -EINVAL; in gpio_rt1718s_pin_config()
61 /* Configure pin as input. */ in gpio_rt1718s_pin_config()
[all …]
Dgpio_shell.c6 * SPDX-License-Identifier: Apache-2.0
20 #define NGPIOS_UNKNOWN -1
23 /* Pin syntax maximum length */
38 gpio_pin_t pin; member
41 * Find idx-th pin reference from the set of non reserved
42 * pin numbers and provided line names.
50 gpio_pin_t pin; in port_pin_get() local
53 entry->handler = NULL; in port_pin_get()
55 /* Find allowed numeric pin reference */ in port_pin_get()
56 for (pin = 0; pin < GPIO_MAX_PINS_PER_PORT; pin++) { in port_pin_get()
[all …]
Dgpio_pca95xx.c6 * SPDX-License-Identifier: Apache-2.0
12 * @file Driver for PCA95XX and PCAL95XX I2C-based GPIO driver.
98 /* Self-reference to the driver instance */
104 /* interrupt triggering pin masks */
120 static int read_port_reg(const struct device *dev, uint8_t reg, uint8_t pin, in read_port_reg() argument
123 const struct gpio_pca95xx_config * const config = dev->config; in read_port_reg()
125 int ret; in read_port_reg()
127 if (pin >= 8) { in read_port_reg()
131 ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf); in read_port_reg()
134 config->bus.addr, reg, ret); in read_port_reg()
[all …]
Dgpio_imx.c2 * Copyright (c) 2018-2019, NXP
4 * SPDX-License-Identifier: Apache-2.0
36 static int imx_gpio_configure(const struct device *port, gpio_pin_t pin, in imx_gpio_configure() argument
39 const struct imx_gpio_config *config = port->config; in imx_gpio_configure()
40 GPIO_Type *base = config->base; in imx_gpio_configure()
43 return -ENOTSUP; in imx_gpio_configure()
45 __ASSERT_NO_MSG(pin < config->mux_count); in imx_gpio_configure()
48 /* Set appropriate bits in pin configuration register */ in imx_gpio_configure()
50 (volatile uint32_t *)config->pin_muxes[pin].config_register; in imx_gpio_configure()
62 return -ENOTSUP; in imx_gpio_configure()
[all …]
/Zephyr-latest/include/zephyr/drivers/adc/
Dads114s0x.h4 * SPDX-License-Identifier: Apache-2.0
13 int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value);
15 int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin);
17 int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin);
19 int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin,
22 int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin,
25 int ads114s0x_gpio_port_get_raw(const struct device *dev,
28 int ads114s0x_gpio_port_set_masked_raw(const struct device *dev,
32 int ads114s0x_gpio_port_toggle_bits(const struct device *dev,
/Zephyr-latest/samples/subsys/tracing/src/
Dtracing_user.c4 * SPDX-License-Identifier: Apache-2.0
11 static int nested_interrupts[CONFIG_MP_MAX_NUM_CPUS];
15 unsigned int key = irq_lock(); in sys_trace_thread_switched_in_user()
17 __ASSERT_NO_MSG(nested_interrupts[_current_cpu->id] == 0); in sys_trace_thread_switched_in_user()
26 unsigned int key = irq_lock(); in sys_trace_thread_switched_out_user()
28 __ASSERT_NO_MSG(nested_interrupts[_current_cpu->id] == 0); in sys_trace_thread_switched_out_user()
37 unsigned int key = irq_lock(); in sys_trace_isr_enter_user()
40 printk("%s: %d\n", __func__, nested_interrupts[curr_cpu->id]); in sys_trace_isr_enter_user()
41 nested_interrupts[curr_cpu->id]++; in sys_trace_isr_enter_user()
48 unsigned int key = irq_lock(); in sys_trace_isr_exit_user()
[all …]
/Zephyr-latest/dts/bindings/spi/
Dnxp,flexio-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,flexio-spi"
8 include: [spi-controller.yaml, "pinctrl-device.yaml"]
11 sdo-pin:
12 type: int
15 Pin select for data output.
17 sdi-pin:
18 type: int
21 Pin select for data input.
23 sck-pin:
[all …]
/Zephyr-latest/include/zephyr/drivers/gpio/
Dgpio_emul.h4 * SPDX-License-Identifier: Apache-2.0
28 * Behaviour of emulated GPIO is application-defined. As-such, each
31 * - define a Device Tree overlay file to indicate the number of GPIO
33 * - register a callback with the GPIO controller using
35 * - asynchronously call @ref gpio_emul_input_set and / or
54 * @return -EINVAL if an invalid argument is provided
56 int gpio_emul_input_set_masked(const struct device *port, gpio_port_pins_t pins,
60 * @brief Modify the value of one emulated GPIO input @p pin
63 * @param pin The pin to modify
64 * @param value New values to assign to @p pin
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.c5 * SPDX-License-Identifier: Apache-2.0
9 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
16 int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func) in soc_port_pinmux_set() argument
18 bool is_odd = pin & 1; in soc_port_pinmux_set()
19 int idx = pin / 2U; in soc_port_pinmux_set()
22 * even numbered pin goes in the bits 0..3 and the odd in soc_port_pinmux_set()
23 * numbered pin in bits 4..7. in soc_port_pinmux_set()
26 pg->PMUX[idx].bit.PMUXO = func; in soc_port_pinmux_set()
28 pg->PMUX[idx].bit.PMUXE = func; in soc_port_pinmux_set()
30 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
[all …]
/Zephyr-latest/dts/bindings/net/wireless/
Dgeneric-fem-two-ctrl-pins.yaml1 # Copyright (c) 2020-2021 Nordic Semiconductor ASA
2 # SPDX-License-Identifier: Apache-2.0
5 This is a representation of generic radio Front-End Module (FEM)
6 that has a two-pin control interface (CTX, CRX).
8 The CTX control pin is used to enable the Power Amplifier (PA) in
10 the "PA pin" in other contexts.
12 The CRX control pin is used to enable the Low Noise Amplifier
14 the "LNA pin" in other contexts.
17 (Though if you do specify a pin, you must also specify its
18 corresponding settle-time-us property.)
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_eos_s3.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
34 static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) in pinctrl_eos_s3_input_selection() argument
39 return -EINVAL; in pinctrl_eos_s3_input_selection()
42 *reg = pin; in pinctrl_eos_s3_input_selection()
50 static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) in pinctrl_eos_s3_set() argument
54 if (pin > IO_MUX_REG_MAX_OFFSET) { in pinctrl_eos_s3_set()
55 return -EINVAL; in pinctrl_eos_s3_set()
57 reg += pin; in pinctrl_eos_s3_set()
63 static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_eos_s3_configure_pin() argument
[all …]
/Zephyr-latest/dts/bindings/ethernet/
Dsilabs,gecko-ethernet.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "silabs,gecko-ethernet"
9 include: ethernet-controller.yaml
21 phy-address:
22 type: int
27 location-rmii:
28 type: int
33 location-mdio:
34 type: int
39 location-phy_mdc:
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_sam0_eic.c4 * SPDX-License-Identifier: Apache-2.0
16 uint8_t pin : 5; member
34 while (EIC->SYNCBUSY.reg) { in wait_synchronization()
37 while (EIC->STATUS.bit.SYNCBUSY) { in wait_synchronization()
45 EIC->CTRLA.bit.ENABLE = on; in set_eic_enable()
47 EIC->CTRL.bit.ENABLE = on; in set_eic_enable()
53 struct sam0_eic_data *const dev_data = dev->data; in sam0_eic_isr()
54 uint16_t bits = EIC->INTFLAG.reg; in sam0_eic_isr()
58 EIC->INTFLAG.reg = bits; in sam0_eic_isr()
74 * Map the EIC lines to the port pin masks based on which port is in sam0_eic_isr()
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Generic pin configuration schema
7 Many data items that are represented in a pin configuration node are
8 common and generic. Pin control bindings should use the properties
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
21 description: disable any pin bias
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dgpio.h2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
5 * Copyright (c) 2015-2016 Intel Corporation.
7 * SPDX-License-Identifier: Apache-2.0
27 #include <zephyr/dt-bindings/gpio/gpio.h>
47 /** Enables pin as input. */
50 /** Enables pin as output, no change to the output state. */
53 /** Disables pin for both input and output. */
69 /** Configures GPIO pin as output and initializes it to a low state. */
71 /** Configures GPIO pin as output and initializes it to a high state. */
73 /** Configures GPIO pin as output and initializes it to a logic 0. */
[all …]
/Zephyr-latest/dts/bindings/video/
Dnxp,video-smartdma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,video-smartdma"
8 include: [base.yaml, pinctrl-device.yaml]
15 vsync-pin:
17 type: int
19 GPIO0 pin index to use for VSYNC input. Only pins 0-15 may be used.
20 hsync-pin:
22 type: int
24 GPIO0 pin index to use for HSYNC input. Only pins 0-15 may be used.
25 pclk-pin:
[all …]

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