2  * Copyright (c) 2018-2019, NXP
4  * SPDX-License-Identifier: Apache-2.0
36 static int imx_gpio_configure(const struct device *port, gpio_pin_t pin,  in imx_gpio_configure()  argument
39 	const struct imx_gpio_config *config = port->config;  in imx_gpio_configure()
40 	GPIO_Type *base = config->base;  in imx_gpio_configure()
43 		return -ENOTSUP;  in imx_gpio_configure()
45 	__ASSERT_NO_MSG(pin < config->mux_count);  in imx_gpio_configure()
48 	/* Set appropriate bits in pin configuration register */  in imx_gpio_configure()
50 		(volatile uint32_t *)config->pin_muxes[pin].config_register;  in imx_gpio_configure()
62 		return -ENOTSUP;  in imx_gpio_configure()
76 		/* Set pin to highz */  in imx_gpio_configure()
83 	/* Init pin configuration struct, and use pinctrl api to apply settings */  in imx_gpio_configure()
84 	__ASSERT_NO_MSG(pin < config->mux_count);  in imx_gpio_configure()
86 	memcpy(&pin_cfg.pinmux, &config->pin_muxes[pin], sizeof(pin_cfg.pinmux));  in imx_gpio_configure()
88 	unsigned int key = irq_lock();  in imx_gpio_configure()
94 	/* Disable interrupts for pin */  in imx_gpio_configure()
95 	GPIO_SetPinIntMode(base, pin, false);  in imx_gpio_configure()
96 	GPIO_SetIntEdgeSelect(base, pin, false);  in imx_gpio_configure()
99 		/* Set output pin initial value */  in imx_gpio_configure()
101 			GPIO_WritePinOutput(base, pin, gpioPinClear);  in imx_gpio_configure()
103 			GPIO_WritePinOutput(base, pin, gpioPinSet);  in imx_gpio_configure()
106 		/* Set pin as output */  in imx_gpio_configure()
107 		WRITE_BIT(base->GDIR, pin, 1U);  in imx_gpio_configure()
109 		/* Set pin as input */  in imx_gpio_configure()
110 		WRITE_BIT(base->GDIR, pin, 0U);  in imx_gpio_configure()
118 static int imx_gpio_port_get_raw(const struct device *port, uint32_t *value)  in imx_gpio_port_get_raw()
120 	const struct imx_gpio_config *config = port->config;  in imx_gpio_port_get_raw()
121 	GPIO_Type *base = config->base;  in imx_gpio_port_get_raw()
128 static int imx_gpio_port_set_masked_raw(const struct device *port,  in imx_gpio_port_set_masked_raw()
132 	const struct imx_gpio_config *config = port->config;  in imx_gpio_port_set_masked_raw()
133 	GPIO_Type *base = config->base;  in imx_gpio_port_set_masked_raw()
135 	unsigned int key = irq_lock();  in imx_gpio_port_set_masked_raw()
143 static int imx_gpio_port_set_bits_raw(const struct device *port,  in imx_gpio_port_set_bits_raw()
146 	const struct imx_gpio_config *config = port->config;  in imx_gpio_port_set_bits_raw()
147 	GPIO_Type *base = config->base;  in imx_gpio_port_set_bits_raw()
149 	unsigned int key = irq_lock();  in imx_gpio_port_set_bits_raw()
156 static int imx_gpio_port_clear_bits_raw(const struct device *port,  in imx_gpio_port_clear_bits_raw()
159 	const struct imx_gpio_config *config = port->config;  in imx_gpio_port_clear_bits_raw()
160 	GPIO_Type *base = config->base;  in imx_gpio_port_clear_bits_raw()
162 	unsigned int key = irq_lock();  in imx_gpio_port_clear_bits_raw()
169 static int imx_gpio_port_toggle_bits(const struct device *port,  in imx_gpio_port_toggle_bits()
172 	const struct imx_gpio_config *config = port->config;  in imx_gpio_port_toggle_bits()
173 	GPIO_Type *base = config->base;  in imx_gpio_port_toggle_bits()
175 	unsigned int key = irq_lock();  in imx_gpio_port_toggle_bits()
182 static int imx_gpio_pin_interrupt_configure(const struct device *port,  in imx_gpio_pin_interrupt_configure()
183 					    gpio_pin_t pin,  in imx_gpio_pin_interrupt_configure()  argument
187 	const struct imx_gpio_config *config = port->config;  in imx_gpio_pin_interrupt_configure()
188 	GPIO_Type *base = config->base;  in imx_gpio_pin_interrupt_configure()
190 	unsigned int key;  in imx_gpio_pin_interrupt_configure()
194 	if (((base->GDIR & BIT(pin)) != 0U)  in imx_gpio_pin_interrupt_configure()
196 		/* Interrupt on output pin not supported */  in imx_gpio_pin_interrupt_configure()
197 		return -ENOTSUP;  in imx_gpio_pin_interrupt_configure()
212 	if (pin < 16U) {  in imx_gpio_pin_interrupt_configure()
213 		shift = 2U * pin;  in imx_gpio_pin_interrupt_configure()
214 		icr_reg = &(base->ICR1);  in imx_gpio_pin_interrupt_configure()
215 	} else if (pin < 32U) {  in imx_gpio_pin_interrupt_configure()
216 		shift = 2U * (pin - 16U);  in imx_gpio_pin_interrupt_configure()
217 		icr_reg = &(base->ICR2);  in imx_gpio_pin_interrupt_configure()
219 		return -EINVAL;  in imx_gpio_pin_interrupt_configure()
226 	WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);  in imx_gpio_pin_interrupt_configure()
227 	WRITE_BIT(base->ISR, pin, mode != GPIO_INT_MODE_DISABLED);  in imx_gpio_pin_interrupt_configure()
228 	WRITE_BIT(base->IMR, pin, mode != GPIO_INT_MODE_DISABLED);  in imx_gpio_pin_interrupt_configure()
235 static int imx_gpio_manage_callback(const struct device *port,  in imx_gpio_manage_callback()
238 	struct imx_gpio_data *data = port->data;  in imx_gpio_manage_callback()
240 	return gpio_manage_callback(&data->callbacks, cb, set);  in imx_gpio_manage_callback()
245 	const struct imx_gpio_config *config = port->config;  in imx_gpio_port_isr()
246 	struct imx_gpio_data *data = port->data;  in imx_gpio_port_isr()
249 	int_status = config->base->ISR & config->base->IMR;  in imx_gpio_port_isr()
251 	config->base->ISR = int_status;  in imx_gpio_port_isr()
253 	gpio_fire_callbacks(&data->callbacks, port, int_status);  in imx_gpio_port_isr()
279 	static int imx_gpio_##n##_init(const struct device *port);	\
301 	static int imx_gpio_##n##_init(const struct device *port)	\