| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.stm32_hal | 1 # STM32 HAL Ethernet driver configuration options
5 # SPDX-License-Identifier: Apache-2.0
8 bool "STM32 HAL Ethernet driver"
19 Enable STM32 HAL based Ethernet driver. It is available for
25 prompt "STM32Cube HAL Ethernet version"
28 bool "Use official STM32Cube HAL driver"
31 Use the official STM32Cube HAL driver instead of the legacy one.
34 bool "Use legacy STM32Cube HAL driver"
37 Driver version based on legacy HAL version as the current official API version.
84 PHY's carrier status is re-evaluated.
[all …]
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| /Zephyr-latest/drivers/crypto/ |
| D | Kconfig.nrf_ecb | 4 # SPDX-License-Identifier: Apache-2.0
11 # (see subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/ecb.c),
15 Enable nRF HAL-based AES ECB encryption driver
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| D | Kconfig.stm32 | 3 # Copyright (c) 2020 Markus Fuchs <markus.fuchs@de.sauter-bc.com>
4 # SPDX-License-Identifier: Apache-2.0
13 Enable STM32 HAL-based Cryptographic Accelerator driver.
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| /Zephyr-latest/soc/st/stm32/common/ |
| D | stm32cube_hal.c | 2 * Copyright (c) 2018, I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Zephyr's implementation for STM32Cube HAL core initialization
11 * STM32Cube HAL in order to be overwritten in case of other
19 * Cube HAL expects a 1ms tick which matches with k_uptime_get_32.
21 * @return HAL status
29 * @brief This function provides minimum delay (in milliseconds) based
41 * @brief Generates an assert on STM32Cube HAL/LL assert trigger.
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| /Zephyr-latest/soc/silabs/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
18 Set if the Back-Up Real Time Counter (BURTC) HAL module is used.
24 Set if the Core interrupt handling (CORE) HAL module is used.
29 Set if the Analog to Digital Converter (ADC) HAL module is used.
34 Set if the Incremental Analog to Digital Converter (IADC) HAL module is used.
39 Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used.
44 Set if the Energy Management Unit (EMU) HAL module is used.
49 Set if the General Purpose Input/Output (GPIO) HAL module is used.
54 Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used.
59 Set if the Low Energy Timer (LETIMER) HAL module is used.
[all …]
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| /Zephyr-latest/soc/st/stm32/stm32f3x/ |
| D | soc.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * Based on reference manual:
12 * STM32F398xE advanced ARM(r)-based MCUs
13 * STM32F37xx advanced ARM(r)-based MCUs
26 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.mec5 | 2 # SPDX-License-Identifier: Apache-2.0
5 bool "Microchip MEC5 HAL kernel timer"
14 The 32-bit 32 KHz based RTOS timer which is operational in
15 full power and deep sleep. Basic timer 5 is a 48 MHz based
16 32-bit down counter with frequency divider used for the
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| /Zephyr-latest/soc/st/stm32/stm32f2x/ |
| D | soc.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * Based on reference manual:
11 * stm32f2X advanced ARM ® -based 32-bit MCUs
24 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/soc/st/stm32/stm32f0x/ |
| D | soc.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * Based on reference manual:
12 * STM32F070x6/xB advanced ARM ® -based MCUs
25 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/soc/st/stm32/stm32f1x/ |
| D | soc.h | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
10 * Based on reference manual:
12 * advanced ARM(r)-based 32-bit MCUs
25 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/soc/st/stm32/stm32f7x/ |
| D | soc.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * Based on reference manual:
12 * advanced ARM(r)-based 32-bit MCUs
24 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/soc/st/stm32/stm32f4x/ |
| D | soc.h | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
5 * SPDX-License-Identifier: Apache-2.0
11 * Based on reference manual:
13 * advanced ARM(r)-based 32-bit MCUs
25 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/soc/st/stm32/stm32l4x/ |
| D | soc.h | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
5 * SPDX-License-Identifier: Apache-2.0
11 * Based on reference manual:
13 * STM32l4x6 advanced ARM(r)-based 32-bit MCUs
26 /* The STM32 HAL headers define these, but they conflict with the Zephyr can.h */
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| /Zephyr-latest/ |
| D | west.yml | 3 # The per-installation west configuration file, .west/config, sets the
22 - name: upstream
23 url-base: https://github.com/zephyrproject-rtos
24 - name: babblesim
25 url-base: https://github.com/BabbleSim
27 group-filter: [-babblesim, -optional]
30 # Please add items below based on alphabetical order
31 # zephyr-keep-sorted-start re(^\s+\- name:)
33 - name: acpica
36 - name: babblesim_base
[all …]
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| /Zephyr-latest/soc/nordic/nrf54l/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level hardware
16 #include <zephyr/dt-bindings/regulator/nrf5x.h>
22 #include <zephyr/dt-bindings/regulator/nrf5x.h>
26 #include <hal/nrf_glitchdet.h>
27 #include <hal/nrf_oscillators.h>
28 #include <hal/nrf_power.h>
29 #include <hal/nrf_regulators.h>
55 uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM; in nordicsemi_nrf54l_init()
63 uint32_t slope_sign_k = (slope_mask_k - (slope_mask_k >> 1)); in nordicsemi_nrf54l_init()
[all …]
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_led_esp32.c | 5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
11 #include <hal/ledc_hal.h>
12 #include <hal/ledc_types.h>
37 ledc_hal_context_t hal; member
64 (struct pwm_ledc_esp32_config *) dev->config; in get_channel_config()
66 for (uint8_t i = 0; i < config->channel_len; i++) { in get_channel_config()
67 if (config->channel_config[i].idx == channel_id) { in get_channel_config()
68 return &config->channel_config[i]; in get_channel_config()
76 struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data; in pwm_led_esp32_low_speed_update()
[all …]
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| /Zephyr-latest/boards/wemos/esp32s2_lolin_mini/doc/ |
| D | index.rst | 6 ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be s…
7 cost-effective, with a high performance and a rich set of IO capabilities. [1]_
11 - RSA-3072-based secure boot
12 - AES-XTS-256-based flash encryption
13 - Protected private key and device secrets from software access
14 - Cryptographic accelerators for enhanced performance
15 - Protection against physical fault injection attacks
16 - Various peripherals:
18 - 43x programmable GPIOs
19 - 14x configurable capacitive touch GPIOs
[all …]
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/ |
| D | radio_nrf5_fem.h | 4 * SPDX-License-Identifier: Apache-2.0
8 * Generic helper macros for getting radio front-end module (FEM)
12 * properties to the generic macros required by the nRF5 radio HAL.
16 #include <zephyr/dt-bindings/gpio/gpio.h>
32 * Device-specific settings are pulled in based FEM_NODE's compatible
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mcux_pcc.c | 4 * Based on clock_control_rv32m1_pcc.c, which is:
7 * SPDX-License-Identifier: Apache-2.0
27 #define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address)
39 cfg = dev->config; in get_clock_encoding()
42 if (!cfg->clock_num) { in get_clock_encoding()
48 if (clock_name >= cfg->clock_num) { in get_clock_encoding()
49 return -EINVAL; in get_clock_encoding()
52 *clock_encoding = cfg->clocks[clock_name]; in get_clock_encoding()
132 * from the HAL. For these SOCs, the clock ID will be built based
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| /Zephyr-latest/soc/atmel/sam/same70/ |
| D | soc.c | 3 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
42 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
67 * TODO: set FWS based on the actual MCK frequency and VDDIO value in clock_init()
70 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
122 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
146 /* Check that the CHIP CIDR matches the HAL one */ in soc_early_init_hook()
147 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
148 LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", in soc_early_init_hook()
[all …]
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| /Zephyr-latest/soc/atmel/sam/samv71/ |
| D | soc.c | 3 * Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
40 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
65 * TODO: set FWS based on the actual MCK frequency and VDDIO value in clock_init()
68 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
119 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
143 /* Check that the CHIP CIDR matches the HAL one */ in soc_early_init_hook()
144 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
145 LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", in soc_early_init_hook()
[all …]
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/ |
| D | ull_chan.c | 4 * SPDX-License-Identifier: Apache-2.0
19 #include "hal/ccm.h"
39 * periodic, and isochronous physical channels based on its local information.
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| /Zephyr-latest/boards/kincony/kincony_kc868_a32/doc/ |
| D | index.rst | 6 Kincony KC868-A32 is a home automation relay module based on the
7 Espressif ESP-WROOM-32 module with all its inherent capabilities
8 (Wi-Fi, Bluetooth, etc.)
12 - 32 digital optoisolated inputs “dry contact”
13 - 4 analog inputs 0-5 V
14 - 32 relays 220 V, 10 A (COM, NO, NC)
15 - RS485 interface
16 - I2C connector
17 - Connector GSM/HMI
18 - Ethernet LAN8270A
[all …]
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | espressif,esp32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 states are composed by groups of pre-defined pin muxing definitions and user
10 Each Zephyr-based application has its own set of pin muxing/pin configuration
11 requirements. The next steps use ESP-WROVER-KIT's I2C_0 to illustrate how one
12 could change a node's pin state properties. Though based on a particular board,
15 Suppose an application running on top of the ESP-WROVER-KIT board, for some
18 you'll notice that the I2C_0 node is already assigned to a pre-defined state.
22 #include "esp_wrover_kit-pinctrl.dtsi"
26 pinctrl-0 = <&i2c0_default>;
27 pinctrl-names = "default";
[all …]
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| /Zephyr-latest/boards/franzininho/esp32s2_franzininho/doc/ |
| D | index.rst | 6 …ho is an educational development board based on ESP32-S2 which is a highly integrated, low-power, …
7 designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities…
11 - RSA-3072-based secure boot
12 - AES-XTS-256-based flash encryption
13 - Protected private key and device secrets from software access
14 - Cryptographic accelerators for enhanced performance
15 - Protection against physical fault injection attacks
16 - Various peripherals:
18 - 43x programmable GPIOs
19 - 14x configurable capacitive touch GPIOs
[all …]
|
