1 /*
2 * Copyright (c) 2019 Vestas Wind Systems A/S
3 *
4 * Based on clock_control_rv32m1_pcc.c, which is:
5 * Copyright (c) 2018 Foundries.io
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10 #define DT_DRV_COMPAT nxp_kinetis_pcc
11
12 #include <errno.h>
13 #include <soc.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <fsl_clock.h>
16
17 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
18 #include <zephyr/logging/log.h>
19 LOG_MODULE_REGISTER(clock_control_mcux_pcc);
20
21 struct mcux_pcc_config {
22 uint32_t base_address;
23 uint32_t *clocks;
24 uint32_t clock_num;
25 };
26
27 #define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address)
28 #ifndef MAKE_PCC_REGADDR
29 #define MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
30 #endif
31
get_clock_encoding(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * clock_encoding)32 static inline int get_clock_encoding(const struct device *dev,
33 clock_control_subsys_t sub_system,
34 uint32_t *clock_encoding)
35 {
36 const struct mcux_pcc_config *cfg;
37 uint32_t clock_name;
38
39 cfg = dev->config;
40 clock_name = POINTER_TO_UINT(sub_system);
41
42 if (!cfg->clock_num) {
43 *clock_encoding = MAKE_PCC_REGADDR(DEV_BASE(dev), clock_name);
44 return 0;
45 }
46
47 /* sanity check */
48 if (clock_name >= cfg->clock_num) {
49 return -EINVAL;
50 }
51
52 *clock_encoding = cfg->clocks[clock_name];
53
54 return 0;
55 }
56
mcux_pcc_on(const struct device * dev,clock_control_subsys_t sub_system)57 static int mcux_pcc_on(const struct device *dev,
58 clock_control_subsys_t sub_system)
59 {
60 uint32_t clock_encoding;
61 int ret;
62
63 ret = get_clock_encoding(dev, sub_system, &clock_encoding);
64 if (ret < 0) {
65 return ret;
66 }
67
68 CLOCK_EnableClock(clock_encoding);
69
70 return 0;
71 }
72
mcux_pcc_off(const struct device * dev,clock_control_subsys_t sub_system)73 static int mcux_pcc_off(const struct device *dev,
74 clock_control_subsys_t sub_system)
75 {
76 uint32_t clock_encoding;
77 int ret;
78
79 ret = get_clock_encoding(dev, sub_system, &clock_encoding);
80 if (ret < 0) {
81 return ret;
82 }
83
84 CLOCK_DisableClock(clock_encoding);
85
86 return 0;
87 }
88
mcux_pcc_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)89 static int mcux_pcc_get_rate(const struct device *dev,
90 clock_control_subsys_t sub_system,
91 uint32_t *rate)
92 {
93 uint32_t clock_encoding;
94 int ret;
95
96 ret = get_clock_encoding(dev, sub_system, &clock_encoding);
97 if (ret < 0) {
98 return ret;
99 }
100
101 *rate = CLOCK_GetIpFreq(clock_encoding);
102
103 return 0;
104 }
105
106 static DEVICE_API(clock_control, mcux_pcc_api) = {
107 .on = mcux_pcc_on,
108 .off = mcux_pcc_off,
109 .get_rate = mcux_pcc_get_rate,
110 };
111
mcux_pcc_init(const struct device * dev)112 static int mcux_pcc_init(const struct device *dev)
113 {
114 #ifdef CONFIG_SOC_MIMX8UD7
115 /* 8ULP's XTAL is set to 24MHz on EVK9. We keep
116 * this as SOC level because this should also be
117 * the case for the EVK board.
118 */
119 CLOCK_SetXtal0Freq(24000000);
120 #endif /* CONFIG_SOC_MIMX8UD7 */
121 return 0;
122 }
123
124 #ifdef CONFIG_SOC_MIMX8UD7
125 static uint32_t clocks[] = {
126 /* clocks managed through PCC4 */
127 kCLOCK_Lpuart7,
128 };
129 #else
130 /* this is empty for SOCs which don't need a translation from
131 * the clock ID passed through the DTS and the clock ID encoding
132 * from the HAL. For these SOCs, the clock ID will be built based
133 * on the value passed from the DTS and the PCC base.
134 */
135 static uint32_t clocks[] = {};
136 #endif /* CONFIG_SOC_MIMX8UD7 */
137
138 #define MCUX_PCC_INIT(inst) \
139 static const struct mcux_pcc_config mcux_pcc##inst##_config = { \
140 .base_address = DT_INST_REG_ADDR(inst), \
141 .clocks = clocks, \
142 .clock_num = ARRAY_SIZE(clocks), \
143 }; \
144 \
145 DEVICE_DT_INST_DEFINE(inst, \
146 mcux_pcc_init, \
147 NULL, \
148 NULL, &mcux_pcc##inst##_config, \
149 PRE_KERNEL_1, \
150 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
151 &mcux_pcc_api);
152
153 DT_INST_FOREACH_STATUS_OKAY(MCUX_PCC_INIT)
154
