Home
last modified time | relevance | path

Searched full:gp (Results 1 – 25 of 36) sorted by relevance

12

/Zephyr-latest/tests/arch/riscv/userspace/riscv_gp/src/
Dmain.c25 uintptr_t gp_val = reg_read(gp); in rogue_user_fn()
28 /* Make sure that `gp` is as expected */ in rogue_user_fn()
35 /* Corrupt `gp` reg */ in rogue_user_fn()
36 reg_write(gp, 0xbad); in rogue_user_fn()
38 /* Make sure that `gp` is corrupted */ in rogue_user_fn()
40 zassert_equal(reg_read(gp), 0xbad); in rogue_user_fn()
45 /* Sleep to force a context switch, which will sanitize `gp` */ in rogue_user_fn()
48 /* Make sure that `gp` is sane again */ in rogue_user_fn()
60 uintptr_t gp_val = reg_read(gp); in ZTEST_USER()
71 /* Create and run a rogue thread to corrupt the `gp` */ in ZTEST_USER()
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ambiq.c37 pin_config.GP.cfg_b.uFuncSel = pin->alt_func; in pinctrl_configure_pin()
38 pin_config.GP.cfg_b.eGPInput = in pinctrl_configure_pin()
40 pin_config.GP.cfg_b.eGPOutCfg = pin->push_pull ? AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL in pinctrl_configure_pin()
44 pin_config.GP.cfg_b.eDriveStrength = pin->drive_strength; in pinctrl_configure_pin()
45 pin_config.GP.cfg_b.uSlewRate = pin->slew_rate; in pinctrl_configure_pin()
46 pin_config.GP.cfg_b.uNCE = pin->iom_nce; in pinctrl_configure_pin()
47 pin_config.GP.cfg_b.eIntDir = pin->interrupt_direction; in pinctrl_configure_pin()
50 pin_config.GP.cfg_b.ePullup = pin->ambiq_pull_up_ohms + AM_HAL_GPIO_PIN_PULLUP_1_5K; in pinctrl_configure_pin()
52 pin_config.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLDOWN_50K; in pinctrl_configure_pin()
/Zephyr-latest/drivers/gpio/
Dgpio_ambiq.c88 pincfg.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLUP_50K; in ambiq_gpio_pin_configure()
90 pincfg.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLDOWN_50K; in ambiq_gpio_pin_configure()
96 pincfg.GP.cfg_b.eGPOutCfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN; in ambiq_gpio_pin_configure()
98 pincfg.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLUP_50K; in ambiq_gpio_pin_configure()
100 pincfg.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLDOWN_50K; in ambiq_gpio_pin_configure()
104 pincfg.GP.cfg_b.eGPOutCfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; in ambiq_gpio_pin_configure()
112 pincfg.GP.cfg_b.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH; in ambiq_gpio_pin_configure()
116 pincfg.GP.cfg_b.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW; in ambiq_gpio_pin_configure()
172 if (pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_DISABLE && in ambiq_gpio_get_config()
173 pincfg.GP.cfg_b.eGPInput == AM_HAL_GPIO_PIN_INPUT_NONE) { in ambiq_gpio_get_config()
[all …]
/Zephyr-latest/drivers/counter/
DKconfig.esp32_tmr7 bool "ESP32 Counter Driver based on GP-Timers"
15 bool "ESP32 Counter Driver based on GP-Timers"
/Zephyr-latest/arch/nios2/core/
Dcrt0.S134 movhi gp, %hi(_gp)
135 ori gp, gp, %lo(_gp)
139 * up. Need to clear r0, write gp, set the exception stack pointer
/Zephyr-latest/arch/riscv/
DKconfig20 prompt "Purpose of the global pointer (GP) register"
33 using GP relative addressing.
36 bool "Store current thread into the global pointer (GP) register"
40 Store the current thread's pointer into the global pointer (GP) register.
159 Selected when SoC has implemented the initialization of global pointer (GP)
160 at program start, or earlier than any instruction using GP relative addressing.
/Zephyr-latest/dts/arm/microchip/mec5/
Dmec5_gpspi_v1.dtsi7 /* Microchip MEC5 MEC172x and MEC5200 GP-SPI controller version 1 hardware
Dmec5_gpspi_v2.dtsi7 /* From Microchip MEC5 MEC174x and onwards use GP-SPI controller version 2 hardware,
/Zephyr-latest/arch/mips/core/
Dfatal.c27 LOG_ERR("$28 : %08lx(gp) (sp) (s8) %08lx(ra)\n", in z_mips_fatal_error()
28 esf->gp, esf->ra); in z_mips_fatal_error()
Disr.S41 op gp, ESF_O(gp)(sp) ;\
/Zephyr-latest/cmake/linker/lld/
Dlinker_flags.cmake21 check_set_linker_property(TARGET linker PROPERTY relax ${LINKERFLAGPREFIX},--relax-gp)
/Zephyr-latest/include/zephyr/arch/nios2/
Dlinker.ld140 PROVIDE(gp = _gp); symbol
218 * accessed globals in a special 64K span of memory addressed by the GP
222 * Since these immediate offsets are signed, place gp 0x8000 past the
228 PROVIDE(gp = _gp); symbol
/Zephyr-latest/include/zephyr/arch/riscv/
Darch_inlines.h31 register struct k_thread *__arch_current_thread __asm__("gp");
/Zephyr-latest/soc/andestech/ae350/
Dstart.S15 /* Disable linker relaxation before GP register initialization. */
Dlinker.ld280 * in a special 4K span of memory addressed by the GP register, then
284 * Since these immediate offsets are signed, place gp 0x800 past the
/Zephyr-latest/arch/mips/core/offsets/
Doffsets.c27 GEN_OFFSET_STRUCT(arch_esf, gp);
/Zephyr-latest/arch/mips/include/mips/
Dregdef.h60 #define gp $28 macro
/Zephyr-latest/soc/ite/ec/common/
Dvector.S22 /* Configure the GP register */
23 la gp, __global_pointer$
/Zephyr-latest/include/zephyr/arch/mips/
Dexception.h22 unsigned long gp; /* global pointer */ member
/Zephyr-latest/arch/nios2/
DKconfig89 Use GP relative access for all data in the program, not just
/Zephyr-latest/dts/bindings/dma/
Dst,stm32u5-dma.yaml7 It is present on stm32U5 devices as a GP DMA
/Zephyr-latest/soc/common/riscv-privileged/
Dvector.S24 la gp, __global_pointer$
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Drisc_v.py20 GP = 3 variable in RegNum
Darm64.py18 X0 = 0 # X0-X29 - 30 GP registers
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dstm32f1-pinctrl.h68 * GPIO Output AF/GP [ 6 ]

12