Searched full:gicd (Results 1 – 10 of 10) sorted by relevance
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_gic_common_priv.h | 10 /* Offsets from GICD base or GICR(n) SGI_base */
24 /* GICD GICR common access macros */
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| D | intc_gicv3.c | 524 /* wait for rwp on GICD */ in gicv3_dist_init()
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| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 14 reg = <0x2f000000 0x10000>, /* GICD */
25 reg = <0x2c010000 0x10000>, /* GICD */
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| /Zephyr-latest/dts/arm64/nxp/ |
| D | nxp_ls1046a.dtsi | 42 reg = <0x01410000 0x10000>, /* GICD */
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| /Zephyr-latest/dts/arm64/rockchip/ |
| D | rk3568.dtsi | 61 reg = <0xfd400000 0x10000>, /* GICD */
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| D | rk3399.dtsi | 54 reg = <0xfee00000 0x10000>, /* GICD */
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| D | rk3588s.dtsi | 70 reg = <0xfe600000 0x10000>, /* GICD */
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| /Zephyr-latest/dts/arm64/ti/ |
| D | ti_am62x_a53.dtsi | 47 reg = <0x01800000 0x10000>, /* GICD */
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| /Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/ |
| D | fvp_base_revc_2xaemv8a.dts | 84 reg = <0x2f000000 0x10000>, // GICD
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| /Zephyr-latest/dts/arm64/intel/ |
| D | intel_socfpga_agilex5.dtsi | 50 reg = <0x1d000000 0x10000>, /* GICD */
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