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/Zephyr-latest/dts/bindings/clock/
Dlitex,clkout.yaml2 # SPDX-License-Identifier: Apache-2.0
13 "#clock-cells":
22 clock-output-names:
28 litex,clock-frequency:
34 litex,clock-phase:
40 litex,clock-duty-num:
44 default duty cycle numerator value
46 litex,clock-duty-den:
50 default duty cycle denominator value
52 litex,clock-margin:
[all …]
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
30 periph-32k-src:
35 xtal-single-ended:
39 clk32kmon-period-min:
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dnxp,s32-emios-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
30 duty-cycle = <32768>;
[all …]
Dinfineon,xmc4xxx-ccu8-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
15 transitions from 0 to 1, preventing the high-side and low-side
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
25 defined by the 'slice-prescaler' property. Additionally, each
38 slice-prescaler = <15 15 15 15>;
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/Zephyr-latest/samples/drivers/clock_control_litex/
DREADME.rst1 .. zephyr:code-sample:: clock-control-litex
3 :relevant-api: clock_control_interface
11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25 :start-at: clk0: clock-controller@0 {
26 :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31 :start-at: clk1: clock-controller@1 {
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/Zephyr-latest/drivers/pwm/
DKconfig.it8xxx24 # SPDX-License-Identifier: Apache-2.0
13 Supports three 16-bit prescalers each with 8-bit cycle timer, and
14 eight PWM channels each with 8-bit duty cycle.
Dpwm_ite_it8801.c4 * SPDX-License-Identifier: Apache-2.0
46 /* PWM duty cycle register */
56 const struct pwm_it8801_config *config = dev->config; in pwm_enable()
60 ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_mcr, in pwm_enable()
63 ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_mcr, in pwm_enable()
88 const struct pwm_it8801_config *config = dev->config; in pwm_it8801_set_cycles()
89 int ch = config->channel, ret; in pwm_it8801_set_cycles()
90 uint8_t duty, mask; in pwm_it8801_set_cycles() local
92 /* Enable PWM output push-pull */ in pwm_it8801_set_cycles()
96 ret = i2c_reg_update_byte_dt(&config->i2c_dev, IT8801_REG_PWMODDSR, mask, mask); in pwm_it8801_set_cycles()
[all …]
Dpwm_mchp_xec_bbled.c4 * SPDX-License-Identifier: Apache-2.0
45 /* BBLED PWM mode uses the duty cycle to set the PWM frequency:
51 * Puse_OFF_width = (1/Fpwm) * (256 - duty_cycle) seconds
52 * where duty_cycle is an 8-bit value 0 to 255.
53 * Prescale is derived from DELAY register LOW_DELAY 12-bit field
54 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
61 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
138 * LIMITS.MIN = duty cycle = [1, 254]
140 * DELAY.LO = pre-scaler = [0, 4095]
147 const struct pwm_bbled_xec_config * const cfg = dev->config; in xec_pwmbb_progam_pwm()
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/Zephyr-latest/include/zephyr/drivers/clock_control/
Dclock_control_litex.h4 * SPDX-License-Identifier: Apache-2.0
34 * @param duty Duty cycle of clock signal in percent
41 uint8_t duty; member
/Zephyr-latest/dts/bindings/sensor/
Dvishay,vcnl4040.yaml2 # SPDX-License-Identifier: Apache-2.0
10 include: [sensor-device.yaml, i2c-device.yaml]
13 int-gpios:
14 type: phandle-array
18 triggered. The sensor generates an active-low level signal
21 led-current:
27 - 50
28 - 75
29 - 100
30 - 120
[all …]
/Zephyr-latest/drivers/clock_control/
DKconfig.litex4 # SPDX-License-Identifier: Apache-2.0
13 such as phase, duty cycle, frequency for up to 7
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
262 return -ETIME; in litex_clk_wait()
303 ldev->g_config.mul = 1; in litex_clk_update_global_config()
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/Zephyr-latest/drivers/led/
Dled_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Microchip Breathing-Blinking LED controller
60 * eight 4-bit fields numbered 0 to 7
107 temp--; in calc_blink_32k_prescaler()
118 /* return duty cycle scaled to [0, 255]
129 * BBLED blinking mode uses an 8-bit accumulator and an 8-bit duty cycle
130 * register. The duty cycle register is programmed once and the
131 * accumulator is used as an 8-bit up counter.
132 * The counter uses the 32768 Hz clock and is pre-scaled by the delay
134 * 8-bit duty cycle values: 0x00 = full off, 0xff = full on.
[all …]
/Zephyr-latest/samples/sensor/vcnl4040/boards/
Dadafruit_feather_stm32f405.overlay4 * SPDX-License-Identifier: Apache-2.0
11 int-gpios = <&feather_header 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
12 led-current = <200>;
13 led-duty-cycle = <320>;
14 proximity-it = "8";
15 proximity-trigger = "close";
16 als-it = <640>;
/Zephyr-latest/drivers/i2c/
Di2c_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
61 volatile uint32_t sclh; /* SCL Duty Cycle */
62 volatile uint32_t scll; /* SCL Duty Cycle */
Di2c_renesas_ra_iic.c4 * SPDX-License-Identifier: Apache-2.0
58 uint32_t duty; member
67 struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data; in i2c_ra_iic_configure()
71 return -EIO; in i2c_ra_iic_configure()
76 data->fsp_config.rate = I2C_MASTER_RATE_STANDARD; in i2c_ra_iic_configure()
79 data->fsp_config.rate = I2C_MASTER_RATE_FAST; in i2c_ra_iic_configure()
82 data->fsp_config.rate = I2C_MASTER_RATE_FASTPLUS; in i2c_ra_iic_configure()
86 return -EIO; in i2c_ra_iic_configure()
90 calc_iic_master_clock_setting(dev, data->fsp_config.rate, in i2c_ra_iic_configure()
91 &data->iic_master_ext_cfg.clock_settings); in i2c_ra_iic_configure()
[all …]
/Zephyr-latest/dts/bindings/i2c/
Drenesas,ra-iic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-iic"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
21 rise-time-ns:
25 fall-time-ns:
29 duty-cycle-percent:
33 interrupt-priority-level:
/Zephyr-latest/boards/nxp/mr_canhubk3/
Dmr_canhubk3.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
27 zephyr,shell-uart = &lpuart2;
[all …]
/Zephyr-latest/drivers/led_strip/
DKconfig.lpd880x2 # SPDX-License-Identifier: Apache-2.0
16 duty cycle can be set at 7 bit resolution via a
/Zephyr-latest/tests/drivers/pwm/pwm_loopback/boards/
Dmr_canhubk3.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
11 compatible = "test-pwm-loopback";
22 input-enable;
29 pinctrl-0 = <&emios0_default>;
30 pinctrl-names = "default";
34 /delete-property/ period;
35 /delete-property/ polarity;
36 /delete-property/ duty-cycle;
38 pwm-mode = "SAIC";
/Zephyr-latest/samples/sensor/sgp40_sht4x/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
17 Maximum duty cycle for using the heater is 5%
31 0 -> High power heater pulse -> ~200 mW @3.3V
32 1 -> Medium power heater pulse -> ~110 mW @3.3V
33 2 -> Low power heater pulse -> ~20 mW @3.3V
41 0 -> Long heater pulse -> 1.1s
42 1 -> Short heater pulse -> 0.11s
/Zephyr-latest/soc/ene/kb1200/reg/
Dfsmbm.h4 * SPDX-License-Identifier: Apache-2.0
41 /* data->state */
90 /* Clock Setting = 1 / (1u + (1u * N)) ,50% Duty Cycle */
110 /* Other(non 50% Duty Cycle) */
/Zephyr-latest/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
25 clk-divider:
30 clk-divider-tc:
35 clk-divider-slow:
40 disable-open-drain-high-pp:
46 so that open drain clock is 50% duty cycle.
/Zephyr-latest/samples/drivers/led/xec/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
76 LOG_ERR("%s: device not ready", dev->name); in led_test()
80 LOG_INF("blink: T = 0.5 second, duty cycle = 0.5"); in led_test()
92 LOG_INF("blink: T = 3 seconds, duty cycle = 0.4"); in led_test()
/Zephyr-latest/samples/kernel/metairq_dispatch/src/
Dmsgdev.h4 * SPDX-License-Identifier: Apache-2.0
25 /* The proc_cyc duty cycle parameters are chosen to use approximately
48 /* Cycle time when the message was "received" */

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