4  * SPDX-License-Identifier: Apache-2.0
11  * @brief Microchip Breathing-Blinking LED controller
60  * eight 4-bit fields numbered 0 to 7
107 		temp--;  in calc_blink_32k_prescaler()
118 /* return duty cycle scaled to [0, 255]
129  * BBLED blinking mode uses an 8-bit accumulator and an 8-bit duty cycle
130  * register. The duty cycle register is programmed once and the
131  * accumulator is used as an 8-bit up counter.
132  * The counter uses the 32768 Hz clock and is pre-scaled by the delay
134  * 8-bit duty cycle values: 0x00 = full off, 0xff = full on.
137  * LoWidth (seconds) = (1/Fblink) * ((1 - duty_cycle) / 256)
138  * duty_cycle in [0, 1]. Register value for duty cycle is
146 	const struct xec_bbled_config * const config = dev->config;  in xec_bbled_blink()
147 	struct xec_bbled_regs * const regs = config->regs;  in xec_bbled_blink()
151 		return -EINVAL;  in xec_bbled_blink()
157 		return -EINVAL;  in xec_bbled_blink()
163 		return -EINVAL;  in xec_bbled_blink()
169 	regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))  in xec_bbled_blink()
171 	regs->delay = (regs->delay & ~(XEC_BBLED_DLY_LO_MSK))  in xec_bbled_blink()
173 	regs->limits = (regs->limits & ~(XEC_BBLED_LIM_MIN_MSK))  in xec_bbled_blink()
175 	regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))  in xec_bbled_blink()
177 	regs->config |= BIT(XEC_BBLED_CFG_EN_UPDATE_POS);  in xec_bbled_blink()
184 	const struct xec_bbled_config * const config = dev->config;  in xec_bbled_on()
185 	struct xec_bbled_regs * const regs = config->regs;  in xec_bbled_on()
188 		return -EINVAL;  in xec_bbled_on()
191 	regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))  in xec_bbled_on()
198 	const struct xec_bbled_config * const config = dev->config;  in xec_bbled_off()
199 	struct xec_bbled_regs * const regs = config->regs;  in xec_bbled_off()
202 		return -EINVAL;  in xec_bbled_off()
205 	regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))  in xec_bbled_off()
213 	const struct xec_bbled_config * const cfg = dev->config;  in xec_bbled_slp_en_clr()
216 	switch (cfg->pcr_pos) {  in xec_bbled_slp_en_clr()
235 	const struct xec_bbled_config * const cfg = dev->config;  in xec_bbled_slp_en_clr()
237 	z_mchp_xec_pcr_periph_sleep(cfg->pcr_id, cfg->pcr_pos, 0);  in xec_bbled_slp_en_clr()
243 	const struct xec_bbled_config * const config = dev->config;  in xec_bbled_init()
244 	struct xec_bbled_regs * const regs = config->regs;  in xec_bbled_init()
250 	regs->config |= BIT(XEC_BBLED_CFG_RST_PWM_POS);  in xec_bbled_init()
251 	regs->config = XEC_BBLED_CFG_MODE_OFF;  in xec_bbled_init()
253 	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);  in xec_bbled_init()