Searched full:div1 (Results 1 – 10 of 10) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | raspberrypi,pico-pll.yaml | 19 post-div1:
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | soc.c | 34 .div1 = kSCG_AsyncClkDivBy1,
57 .div1 = kSCG_AsyncClkDivBy1,
179 .div1 = kSCG_AsyncClkDisable, in rv32m1_switch_to_sirc()
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| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 74 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv1_clk)),
87 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv1_clk)),
105 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv1_clk)),
135 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv1_clk)),
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_xlnx_gem.c | 791 uint32_t div1; in eth_xlnx_gem_configure_clocks() local
832 for (div1 = 1; div1 < 64; div1++) { in eth_xlnx_gem_configure_clocks()
833 tmp = ((dev_conf->pll_clock_frequency / div0) / div1); in eth_xlnx_gem_configure_clocks()
848 * div0 bits [13..8], div1 bits [21..16] in eth_xlnx_gem_configure_clocks()
859 ((div1 & ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR_MASK) << in eth_xlnx_gem_configure_clocks()
885 ((div1 & ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK) << in eth_xlnx_gem_configure_clocks()
892 "frequency %u Hz", dev->name, div0, div1, target); in eth_xlnx_gem_configure_clocks()
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| /Zephyr-latest/dts/arm/raspberrypi/rpi_pico/ |
| D | rp2040.dtsi | 134 post-div1 = <6>;
145 post-div1 = <5>;
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| D | rp2350.dtsi | 130 post-div1 = <5>;
141 post-div1 = <5>;
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | renesas,smartbond-nor-psram.yaml | 129 this block is always DIV1 which reflects the current
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_u5.c | 440 * For HSI16, epod prescaler is default (div1, not divided).
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| D | clock_control_rpi_pico.c | 799 "pll_sys: post-div1 is out of range");
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_esp32.c | 118 * Of the second stage dividers, div0 is used for card 0, and div1 is used
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