| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 14 SoC series (dual core ARM Cortex-A9).
20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
50 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
58 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
66 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/ |
| D | Kconfig.soc | 14 SoC series (single core ARM Cortex-A9).
20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
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| /Zephyr-latest/arch/xtensa/core/ |
| D | window_vectors.S | 126 * a9 is call[j+1]'s stack pointer.
133 s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */
136 s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
137 s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
138 s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */
155 * a9 is call[i+1]'s stack pointer.
162 l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */
163 l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
164 l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
167 l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */
[all …]
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| D | userspace.S | 18 * a2 a6, a3, a4, a5, a8, a9
167 * arg6 = a9
170 mov a11, a9
172 mov a9, a5
329 l32i a9, a1, 8
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| D | crt1.S | 44 # define ARG4 a9 /* 4th outgoing call argument */
159 * a9 = end address of bytes to be zeroed
167 l32i a9, a6, 4 /* get end address, assumed multiple of 4 */
169 sub a10, a9, a8 /* a10 = length, assumed a multiple of 4 */
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| D | syscall_helper.c | 26 register uintptr_t a9 __asm__("%a9") = arg6; in xtensa_syscall_helper_args_6()
31 "r" (a5), "r" (a8), "r" (a9) in xtensa_syscall_helper_args_6()
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| /Zephyr-latest/boards/udoo/udoo_neo_full/doc/ |
| D | index.rst | 8 composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4
11 will also communicate with the Cortex-A9 core (running Linux) via OpenAMP.
16 - MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core
28 - A9 Boot Devices
64 - 32x GPIO (A9)
152 PLL settings for M4 core are set via code running on the A9 core.
158 remaining are used by the A9 core or not used.
164 at power-on-reset. Therefore it needs to be started by the A9 core.
165 The A9 core is responsible to load the M4 binary application into the RAM,
167 the M4 out of reset. The A9 can perform these steps at the bootloader level
[all …]
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | st,stm32f1-pinctrl.yaml | 88 GPIO A9 set as alternate with no remap
92 GPIO A9 set as alternate with full remap
96 GPIO A9 set as input
100 GPIO A9 set as output-high
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| D | st,stm32-pinctrl.yaml | 79 GPIO A9 set as alternate function 2
83 GPIO A9 set as analog
87 GPIO A9 set as GPIO output high
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| /Zephyr-latest/boards/qemu/cortex_a9/ |
| D | qemu_cortex_a9.dts | 12 model = "QEMU Cortex-A9";
22 compatible = "arm,cortex-a9";
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| D | board.yml | 3 full_name: QEMU Emulation for Cortex-A9
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| D | Kconfig | 2 # Kconfig - Cortex-A9 QEMU Emulation
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| D | Kconfig.qemu_cortex_a9 | 2 # Kconfig - Cortex-A9 QEMU Emulation
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| D | qemu_cortex_a9.yaml | 9 name: QEMU Emulation for Cortex-A9
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| D | board.cmake | 9 set(QEMU_CPU_TYPE_${ARCH} cortex-a9)
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| D | Kconfig.defconfig | 2 # Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation
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| /Zephyr-latest/boards/digilent/zybo/ |
| D | zybo.dts | 40 compatible = "arm,cortex-a9";
46 compatible = "arm,cortex-a9";
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| /Zephyr-latest/include/zephyr/arch/xtensa/ |
| D | syscall.h | 57 * a2 a6, a3, a4, a5, a8, a9
76 register uintptr_t a9 __asm__("%a9") = arg6; in arch_syscall_invoke6()
81 "r" (a5), "r" (a8), "r" (a9) in arch_syscall_invoke6()
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| /Zephyr-latest/scripts/coredump/gdbstubs/arch/ |
| D | xtensa.py | 293 A9 = 98 variable in GdbRegDef_Sample_Controller.RegNum
327 A9 = 166 variable in GdbRegDef_ESP32.RegNum
359 A9 = 164 variable in GdbRegDef_ESP32S2.RegNum
389 A9 = 221 variable in GdbRegDef_ESP32S3.RegNum
430 A9 = 167 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
470 A9 = 265 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
505 A9 = 114 variable in GdbRegDef_DC233C.RegNum
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32mp1-rcc.yaml | 6 On STM32MP1 platforms, clock control configuration is performed on A9 side.
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| /Zephyr-latest/arch/xtensa/include/ |
| D | xtensa_asm2_context.h | 60 * - Saved A9 +- If not in-use by another frame
190 uintptr_t a9; member
211 uintptr_t a9; member
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.arm_arch | 23 ARM Cortex-A9 processors Software Developers Errata Notice, ARM
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| /Zephyr-latest/soc/nxp/imx/ |
| D | soc.yml | 50 - name: a9
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| /Zephyr-latest/samples/subsys/llext/modules/ |
| D | sample.yaml | 4 - qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
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| /Zephyr-latest/doc/ |
| D | substitutions.txt | 12 .. |copy| unicode:: U+000A9 .. COPYRIGHT SIGN
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