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/Zephyr-latest/dts/bindings/led_strip/
Dws2812.yaml15 A 0 bit's pulse width is between 200 and 500 ns. A 1 bit's is
16 at least 550 ns, with 700 ns or so typical. Pixel order is GRB.
28 0 bit: 300 ns high and 900 ns low.
29 1 bit: 900 ns high and 300 ns low.
31 There is a +/- 80 ns tolerance for each timing.
42 default: 8
45 latched the signal. If omitted, a default value of 8 microseconds is used.
48 6 microseconds is enough. The default is set to 8 microseconds just to be
/Zephyr-latest/dts/bindings/auxdisplay/
Dhit,hd44780.yaml17 description: Operating mode of display, 8-bit or 4 for 4-bit mode
20 - 8
41 contain 8 entries ascending from DB0 to DB7, for 4-bit interface
59 enable-line-rise-delay-ns:
63 Delay time (in ns) to wait after enable line rises before setting low.
66 enable-line-fall-delay-ns:
70 Delay time (in ns) to wait after enable line falls before sending
73 rs-line-delay-ns:
77 Delay time (in ns) to wait after rs/rw line state has been set up before
/Zephyr-latest/boards/snps/nsim/arc_classic/support/
Dnsim_sem_mpu_stack_guard.props16 nsim_isa_mpy_option=8
35 nsim_isa_smart_stack_entries=8
55 iccm0_sec_lvl=NS
56 dccm_sec_lvl=NS
57 nsim_isa_pct_counters=8
Dnsim_sem.props16 nsim_isa_mpy_option=8
35 nsim_isa_smart_stack_entries=8
55 iccm0_sec_lvl=NS
56 dccm_sec_lvl=NS
57 nsim_isa_pct_counters=8
Dmdb_sem_mpu_stack_guard.args30 -smart_stack_entries=8
50 -iccm0_sec_lvl=NS
51 -dccm_sec_lvl=NS
52 -Xpct_counters=8
Dmdb_sem.args30 -smart_stack_entries=8
50 -iccm0_sec_lvl=NS
51 -dccm_sec_lvl=NS
52 -Xpct_counters=8
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c15 #define DIO8_PIN 8
32 for (i = 0; i < 8; i++) { in CC1352R1_LAUNCHXL_sendExtFlashByte()
42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
44 CPUdelay(8); in CC1352R1_LAUNCHXL_sendExtFlashByte()
64 * least 20 ns and ten wait at least 35 us. in CC1352R1_LAUNCHXL_wakeUpExtFlash()
67 /* Toggle chip select for ~20ns to wake ext. flash */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-latest/subsys/net/l2/ethernet/gptp/
DKconfig47 bool "25ns"
49 bool "100ns"
51 bool "250ns"
121 int "Set neighbor propagation delay threshold (ns)"
177 default 8
180 Announce message. Each array element takes 8 bytes. If this value
181 is set to 8, then 8 * 8 = 64 bytes of memory is used.
/Zephyr-latest/samples/tfm_integration/psa_crypto/
DREADME.rst89 (``-DBOARD=mps2/an521/cpu0/ns``).
96 west build -p -b mps2/an521/cpu0/ns samples/tfm_integration/psa_crypto
105 cmake -GNinja -DBOARD=mps2/an521/cpu0/ns ..
115 cmake -DBOARD=mps2/an521/cpu0/ns ..
142 Build Zephyr with a non-secure configuration (``-DBOARD=mps2/an521/cpu0/ns``)
150 west build -p -b mps2/an521/cpu0/ns samples/tfm_integration/psa_crypto -t run
159 cmake -GNinja -DBOARD=mps2/an521/cpu0/ns ..
169 cmake -DBOARD=mps2/an521/cpu0/ns ..
203 (``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns`` or ``-DBOARD=nrf9160dk/nrf9160/ns``).
212 cmake -GNinja -DBOARD=nrf9160dk/nrf9160/ns ..
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/Zephyr-latest/drivers/disk/nvme/
Dnvme_namespace.h115 uint8_t eui64[8];
175 uint32_t nvme_namespace_get_sector_size(struct nvme_namespace *ns);
177 uint64_t nvme_namespace_get_num_sectors(struct nvme_namespace *ns);
179 uint64_t nvme_namespace_get_size(struct nvme_namespace *ns);
181 uint32_t nvme_namespace_get_flags(struct nvme_namespace *ns);
183 const char *nvme_namespace_get_serial_number(struct nvme_namespace *ns);
185 const char *nvme_namespace_get_model_number(struct nvme_namespace *ns);
188 nvme_namespace_get_data(struct nvme_namespace *ns);
190 uint32_t nvme_namespace_get_stripesize(struct nvme_namespace *ns);
192 int nvme_namespace_construct(struct nvme_namespace *ns,
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/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml36 each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
37 55ns, as per specification, it requires atmel,smc-cycle-timing of at least
38 7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
41 is66wv51216dbll-55 a minimum setup of 5ns (1 cycle) with at least 45ns
150 Effective value for each element: 256 x cycle[8:7] + cycle[6:0]
/Zephyr-latest/tests/benchmarks/wait_queues/src/
Dutils.h17 #define CYCLE_FORMAT "%8u"
18 #define NSEC_FORMAT "%8u"
21 #define CYCLE_FORMAT "%8u cycles"
22 #define NSEC_FORMAT "%8u ns"
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5.h19 #define HAL_RADIO_NS2US_CEIL(ns) ((ns + 999)/1000) argument
20 #define HAL_RADIO_NS2US_ROUND(ns) ((ns + 500)/1000) argument
103 #define HAL_RADIO_PDU_LEN_MAX (BIT(8) - 1)
/Zephyr-latest/dts/bindings/i3c/
Di3c-device.yaml41 * bit[31:8]: unused.
43 * Index 0: I2C device has a 50 ns spike filter where
45 * Index 1: I2C device does not have a 50 ns spike filter
47 * Index 2: I2C device does not have a 50 ns spike filter
/Zephyr-latest/tests/benchmarks/sched_queues/src/
Dutils.h19 #define CYCLE_FORMAT "%8u"
20 #define NSEC_FORMAT "%8u"
23 #define CYCLE_FORMAT "%8u cycles"
24 #define NSEC_FORMAT "%8u ns"
/Zephyr-latest/dts/bindings/fpga/
Dlattice,ice40-fpga-base.yaml30 The datasheet specifies a minimum of 200ns, therefore the default is set
40 default: 8
43 The datasheet specifies 8 dummy cycles, which is the default.
/Zephyr-latest/drivers/led_strip/
Dtlc59731.c13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
21 * A pulse must be high for at least 14ns. In practice, turning a GPIO on
25 * A one is represented by an additional pulse between 275ns and 2.5us
27 * 275ns, but because of the limited granularity of k_busy_wait we use a
48 #define TLC59731_T_H1 (8 * TLC59731_T_CYCLE_0)
/Zephyr-latest/tests/lib/lockfree/src/
Dtest_mpsc.c71 #define MPSC_FREEQ_SZ 8
227 uint64_t ns = timing_cycles_to_ns(cycles); in ZTEST() local
229 TC_PRINT("%llu ns for %d iterations, %llu ns per op\n", ns, in ZTEST()
230 THROUGHPUT_ITERS, ns/THROUGHPUT_ITERS); in ZTEST()
/Zephyr-latest/tests/benchmarks/latency_measure/src/
Dutils.h54 #define CYCLE_FORMAT "%8u"
55 #define NSEC_FORMAT "%8u"
58 #define CYCLE_FORMAT "%8u cycles"
59 #define NSEC_FORMAT "%8u ns"
/Zephyr-latest/dts/bindings/pwm/
Dinfineon,cat1-pwm.yaml56 (8-bit divider) or 1 to 65536 (16-bit divider).
64 - period to set in ns
Despressif,esp32-mcpwm.yaml33 Channel 8 -> Capture 2
89 8 bit timer prescale for the global clock.
90 Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1).
98 8 bit timer prescale for timer 0.
104 8 bit timer prescale for timer 1.
110 8 bit timer prescale for timer 2.
/Zephyr-latest/samples/tfm_integration/tfm_psa_test/
DREADME.rst35 -p -b mps2/an521/cpu0/ns -t run -- \
53 …$ west build samples/tfm_integration/tfm_psa_test/ -p -b mps2/an521/cpu0/ns -t run -- -DCONFIG_TFM…
79 [Check 8] Call get_info API for different UID 5
91 [Check 8] Call get_info API for different UID 5
/Zephyr-latest/samples/drivers/led/pwm/boards/
Dmec15xxevb_assy6853.overlay15 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
16 * 255 full on. BBLED PWM is 8-bit.
25 /* struct pwm_dt_spec: phandle channel period(ns) flags */
/Zephyr-latest/doc/services/storage/nvs/
Dnvs.rst19 Each element is stored in flash as metadata (8 byte) and data. The metadata is
88 Each write of the state variable requires 12 bytes of flash storage: 8 bytes
99 - ``NS`` as the number of storage requests per minute,
106 SECTOR_COUNT * SECTOR_SIZE * PAGE_ERASES / (NS * (DS+8)) minutes
117 Especially, migration between 1,2,4,8-bytes write block sizes is allowed.
/Zephyr-latest/doc/_static/images/
Dlogo-readme-light.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
4 xmlns:cc="http://creativecommons.org/ns#"
5 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
29 …s-6{fill:url(#linear-gradient-3);}.cls-7{fill:url(#linear-gradient-4);}.cls-8{fill:#2d3136;}</styl…
135 class="cls-8"
139 class="cls-8"
143 class="cls-8"
147 class="cls-8"
151 class="cls-8"
155 class="cls-8"
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