| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_i2c_smb.h | 36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
50 #define MCHP_I2C_SMB_STS_LAB BIT(1)
51 #define MCHP_I2C_SMB_STS_AAS BIT(2)
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| D | mec172x_ecia.h | 16 #define MCHP_FIRST_GIRQ_NOS 8u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
35 /* MEC172x implements 8 priority levels. ARM NVIC 0 = highest priority */
41 * External sources are grouped by 32-bit registers.
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| D | mec172x_pcr.h | 56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
88 #define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0)
89 #define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3)
91 * bit[8] can be used to prevent entry to heavy sleep unless the
93 * bit[8]==0 (POR default) system will allow entry to light or heavy
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| D | mec172x_espi_vw.h | 13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
28 /* 32-bit word 1 (bits[63:32]) */
33 #define ESPI_M2SW1_SRC1_SEL_POS 8
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
43 /* 32-bit word 2 (bits[95:64]) */
44 #define ESPI_M2SW2_OFS 8u
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| D | mec172x_p80bd.h | 15 /* HDATA - Write-Only 32-bit */
20 * EC-only Data/Attributes 16-bit
22 * b[15:8] = data attributes
27 #define MCHP_P80BD_ECDA_APOS 8
30 #define MCHP_P80BD_ECDA_LANE_POS 8
42 #define MCHP_P80BD_ECDA_NE BIT(12)
43 #define MCHP_P80BD_ECDA_OVR BIT(13)
44 #define MCHP_P80BD_ECDA_THR BIT(14)
49 #define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */
50 #define MCHP_P80BD_CFG_SNAP_CLR BIT(1) /* WO */
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| D | mec172x_espi_saf.h | 33 /* SAF Protection region described by 4 32-bit registers. 17 regions */
36 /* Register bit definitions */
44 #define MCHP_SAF_ECP_CMD_CTYPE_POS 8
61 #define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24)
62 #define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25)
71 #define MCHP_SAF_ECP_START BIT(0)
81 #define MCHP_SAF_ECP_STS_DONE BIT(0)
82 #define MCHP_SAF_ECP_STS_DONE_TST BIT(1)
83 #define MCHP_SAF_ECP_STS_TMOUT BIT(2)
84 #define MCHP_SAF_ECP_STS_OOR BIT(3)
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| D | mec172x_qspi.h | 38 #define MCHP_QMSPI_TX_FIFO_LEN 8u
39 #define MCHP_QMSPI_RX_FIFO_LEN 8u
49 #define MCHP_QMSPI_EXE_OFS 8u
130 #define MCHP_QMSPI_M_ACTIVATE BIT(0)
131 #define MCHP_QMSPI_M_SRST BIT(1)
132 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2)
133 #define MCHP_QMSPI_M_LDMA_RX_EN BIT(3)
134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
135 #define MCHP_QMSPI_M_CPOL_POS 8u
137 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8)
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| /Zephyr-Core-2.7.6/lib/gui/lvgl/ |
| D | lvgl_display_mono.c | 22 desc.buf_size = (w * h)/8U; in lvgl_flush_cb_mono()
42 uint8_t bit; in lvgl_set_px_cb_mono() local
48 buf_xy = buf + x + y/8 * buf_w; in lvgl_set_px_cb_mono()
51 bit = 7 - y%8; in lvgl_set_px_cb_mono()
53 bit = y%8; in lvgl_set_px_cb_mono()
56 buf_xy = buf + x/8 + y * buf_w/8; in lvgl_set_px_cb_mono()
59 bit = 7 - x%8; in lvgl_set_px_cb_mono()
61 bit = x%8; in lvgl_set_px_cb_mono()
67 *buf_xy &= ~BIT(bit); in lvgl_set_px_cb_mono()
69 *buf_xy |= BIT(bit); in lvgl_set_px_cb_mono()
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| /Zephyr-Core-2.7.6/drivers/ethernet/ |
| D | eth_enc424j600_priv.h | 136 #define ENC424J600_PSFR_PHCON1 (BIT(8) | 0x00)
137 #define ENC424J600_PSFR_PHSTAT1 (BIT(8) | 0x01)
138 #define ENC424J600_PSFR_PHANA (BIT(8) | 0x04)
139 #define ENC424J600_PSFR_PHANLPA (BIT(8) | 0x05)
140 #define ENC424J600_PSFR_PHANE (BIT(8) | 0x06)
141 #define ENC424J600_PSFR_PHCON2 (BIT(8) | 0x11)
142 #define ENC424J600_PSFR_PHSTAT2 (BIT(8) | 0x1B)
143 #define ENC424J600_PSFR_PHSTAT3 (BIT(8) | 0x1F)
195 #define ENC424J600_MICMD_MIIRD BIT(0)
197 #define ENC424J600_MISTAT_BUSY BIT(0)
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| /Zephyr-Core-2.7.6/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 40 IPC_EVENT_BIT(8) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
57 [5] = BIT(5),
58 [6] = BIT(6),
59 [7] = BIT(7),
60 [8] = BIT(8),
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| /Zephyr-Core-2.7.6/dts/bindings/sensor/ |
| D | bosch,bmp388.yaml | 22 3.125 - 25/8 - 320ms
59 1 sample, 16-bit, 2.64 Pa
60 2 samples, 17-bit, 1.32 Pa
61 4 samples, 18-bit, 0.66 Pa (default; chip reset value)
62 8 samples, 19-bit, 0.33 Pa
63 16 samples, 20-bit, 0.17 Pa
64 32 Samples, 21-bit, 0.085 Pa
70 - 8
80 1 sample, 16-bit, .0050 C (default; chip reset value)
81 2 samples, 17-bit, .0025 C
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| D | ti,ina219.yaml | 47 3 = /8 -> ±320 mV
64 0 = 9 bit -> 84 µs
65 1 = 10 bit -> 148 µs
66 2 = 11 bit -> 276 µs
67 3 = 12 bit -> 532 µs
68 9 = 12 bit - 2 sample averaging -> 1.06 ms
69 10 = 12 bit - 4 sample averaging -> 2.13 ms
70 11 = 12 bit - 8 sample averaging -> 4.26 ms
71 12 = 12 bit - 16 sample averaging -> 8.51 ms
72 13 = 12 bit - 32 sample averaging -> 17.02 ms
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_s1000/ |
| D | soc.h | 13 #define CAVS_IRQ_NUM_SHIFT 8
22 * 1. Peripheral Register bit offset.
23 * 2. CAVS logic bit offset.
64 #define DMA_HANDSHAKE_SSP3_TX 8
78 #define SSP_MN_DIV_SIZE (8)
85 #define SOC_MDIVCTRL_MCLK_OUT_EN(mclk) BIT(mclk)
97 #define SOC_NUM_CHANNELS_IN_DMAC 8
103 #define DSP_WCT_CS_TA(x) BIT(x)
104 #define DSP_WCT_CS_TT(x) BIT(4 + x)
108 /* bit field definition for LP GPDMA ownership register */
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| /Zephyr-Core-2.7.6/include/sys/ |
| D | byteorder.h | 20 #define __bswap_16(x) ((uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)))
25 (((x) >> 8) & 0xff00) | \
26 (((x) & 0xff00) << 8) | \
30 (((x) >> 8) & 0xff0000) | \
31 (((x) & 0xff0000) << 8) | \
37 (((x) >> 8) & 0xff000000) | \
38 (((x) & 0xff000000) << 8) | \
44 * @brief Convert 16-bit integer from little-endian to host endianness.
46 * @param val 16-bit integer in little-endian format.
48 * @return 16-bit integer in host endianness.
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| /Zephyr-Core-2.7.6/include/arch/arm64/ |
| D | cpu.h | 12 #define DAIFSET_FIQ_BIT BIT(0)
13 #define DAIFSET_IRQ_BIT BIT(1)
14 #define DAIFSET_ABT_BIT BIT(2)
15 #define DAIFSET_DBG_BIT BIT(3)
17 #define DAIFCLR_FIQ_BIT BIT(0)
18 #define DAIFCLR_IRQ_BIT BIT(1)
19 #define DAIFCLR_ABT_BIT BIT(2)
20 #define DAIFCLR_DBG_BIT BIT(3)
22 #define DAIF_FIQ_BIT BIT(6)
23 #define DAIF_IRQ_BIT BIT(7)
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| /Zephyr-Core-2.7.6/drivers/spi/ |
| D | spi_dw.h | 93 #define DW_SPI_CTRLR0_SCPH BIT(DW_SPI_CTRLR0_SCPH_BIT)
94 #define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT)
95 #define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT)
98 #define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
103 #define DW_SPI_CTRLR0_TMOD_SHIFT (8)
121 /* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
122 * These are the bits were when you divide by 8, you keep the result as it is.
127 (((__bpw) / 8) + 1) : \
128 ((__bpw) / 8))
147 #define DW_SPI_IMR_TXEIM BIT(DW_SPI_IMR_TXEIM_BIT)
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| /Zephyr-Core-2.7.6/include/drivers/interrupt_controller/ |
| D | intc_mchp_xec_ecia.h | 11 * Reference Manuals for MEC152x and MEC172x ARM(r) 32-bit MCUs
26 * @param girq_id is the GIRQ number (8 - 26)
34 * @param girq_id is the GIRQ number (8 - 26)
46 * @param girq_id is the GIRQ number (8 - 26)
68 * @param girq_id is the GIRQ number (8 - 26)
84 * @param girq_id is the GIRQ number (8 - 26)
89 /** @brief clear GIRQ latched source status bit
91 * @param girq_id is the GIRQ number (8 - 26)
92 * @param src_bit is the source bit position in the GIRQ registers (0 - 31)
98 * @param girq_id is the GIRQ number (8 - 26)
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| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/common/reg/ |
| D | mec_adc.h | 14 #define MCHP_ADC_MAX_CHAN 8u
22 #define MCHP_ADC_CTRL_ACTV BIT(0)
23 #define MCHP_ADC_CTRL_START_SNGL BIT(1)
24 #define MCHP_ADC_CTRL_START_RPT BIT(2)
25 #define MCHP_ADC_CTRL_PWRSV_DIS BIT(3)
26 #define MCHP_ADC_CTRL_SRST BIT(4)
27 #define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */
28 #define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */
39 #define MCHP_ADC_STATUS_REG_OFS 8u
41 #define MCHP_ADC_STATUS_CHAN(n) BIT(n)
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| /Zephyr-Core-2.7.6/tests/kernel/common/src/ |
| D | bitarray.c | 16 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
18 #define BIT_INDEX(bit) (bit >> 3) argument
20 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
57 num_bundles = ROUND_UP(ROUND_UP(num_bits, 8) / 8, sizeof(uint32_t)) in validate_bitarray_define()
131 size_t bit, bundle_idx, bit_idx_in_bundle; in test_bitarray_set_clear() local
140 for (bit = 0U; bit < ba.num_bits; ++bit) { in test_bitarray_set_clear()
141 bundle_idx = bit / (sizeof(ba.bundles[0]) * 8); in test_bitarray_set_clear()
142 bit_idx_in_bundle = bit % (sizeof(ba.bundles[0]) * 8); in test_bitarray_set_clear()
144 ret = sys_bitarray_set_bit(&ba, bit); in test_bitarray_set_clear()
146 "sys_bitarray_set_bit failed on bit %d", bit); in test_bitarray_set_clear()
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| /Zephyr-Core-2.7.6/drivers/audio/ |
| D | intel_dmic.h | 29 #define DMIC_HW_CIC_SHIFT_MIN -8
32 #define DMIC_HW_FIR_SHIFT_MAX 8
37 #define DMIC_HW_SENS_Q28 BIT(28) /* 1.0 in Q1.28 format */
75 #define OUTCONTROL0_TIE_BIT BIT(27)
76 #define OUTCONTROL0_SIP_BIT BIT(26)
77 #define OUTCONTROL0_FINIT_BIT BIT(25)
78 #define OUTCONTROL0_FCI_BIT BIT(24)
89 #define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
93 #define OUTCONTROL1_TIE_BIT BIT(27)
94 #define OUTCONTROL1_SIP_BIT BIT(26)
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| /Zephyr-Core-2.7.6/drivers/flash/ |
| D | jesd216.c | 19 res->instr = packed >> 8; in extract_instr()
36 && (sys_le32_to_cpu(bfp->dw10[5]) & BIT(9))) { in jesd216_bfp_read_support()
42 && (sys_le32_to_cpu(bfp->dw10[9]) & BIT(9))) { in jesd216_bfp_read_support()
50 if (sys_le32_to_cpu(bfp->dw1) & BIT(16)) { in jesd216_bfp_read_support()
57 if (sys_le32_to_cpu(bfp->dw1) & BIT(22)) { in jesd216_bfp_read_support()
73 if (sys_le32_to_cpu(bfp->dw1) & BIT(20)) { in jesd216_bfp_read_support()
80 if (sys_le32_to_cpu(bfp->dw1) & BIT(21)) { in jesd216_bfp_read_support()
90 if ((uint8_t)(dw17 >> 8) != 0) { in jesd216_bfp_read_support()
96 if (sys_le32_to_cpu(bfp->dw5) & BIT(0)) { in jesd216_bfp_read_support()
103 if (sys_le32_to_cpu(bfp->dw5) & BIT(4)) { in jesd216_bfp_read_support()
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| /Zephyr-Core-2.7.6/drivers/pinmux/ |
| D | pinmux_b91.c | 17 * gpio_en + 1*8: PORT_B[0-7]
18 * gpio_en + 2*8: PORT_C[0-7]
19 * gpio_en + 3*8: PORT_D[0-7]
20 * gpio_en + 4*8: PORT_E[0-7]
21 * gpio_en + 5*8: PORT_F[0-7]
24 ((pin >> 8) * 8)))
43 (((pin >> 8) < 4) ? ((pin >> 8) * 2) : 0) + \
44 (((pin >> 8) == 4) ? 0x20 : 0) + \
45 (((pin >> 8) == 5) ? 0x26 : 0) + \
59 * pull_up_en + 8: PORT_E[0-3]
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| /Zephyr-Core-2.7.6/include/arch/x86/ |
| D | msr.h | 16 #define X86_SPEC_CTRL_MSR_IBRS BIT(0)
17 #define X86_SPEC_CTRL_MSR_SSBD BIT(2)
20 #define X86_APIC_BASE_MSR_X2APIC BIT(10)
23 #define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)
28 #define X86_EFER_MSR_SCE BIT(0)
29 #define X86_EFER_MSR_LME BIT(8)
30 #define X86_EFER_MSR_NXE BIT(11)
33 * 47:32 Kernel CS (SS = CS+8)
34 * 63:48 User CS (SS = CS+8)
54 * z_x86_msr_write() is shared between 32- and 64-bit implementations, but
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_s1000/soc/ |
| D | shim.h | 24 #ifndef BIT
25 #define BIT(b) (1 << (b)) macro
36 #define IPC_DIPCT_BUSY BIT(31)
43 #define IPC_DIPCI_BUSY BIT(31)
47 #define IPC_DIPCIE_DONE BIT(30)
51 #define IPC_DIPCCTL_IPCIDIE BIT(1)
52 #define IPC_DIPCCTL_IPCTBIE BIT(0)
64 #define IPC_IDCTFC_BUSY BIT(31)
71 #define IPC_IDCITC_BUSY BIT(31)
75 #define IPC_IDCIETC_DONE BIT(30)
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v15/include/soc/ |
| D | shim.h | 24 #ifndef BIT
25 #define BIT(b) (1 << (b)) macro
36 #define IPC_DIPCT_BUSY BIT(31)
43 #define IPC_DIPCI_BUSY BIT(31)
47 #define IPC_DIPCIE_DONE BIT(30)
51 #define IPC_DIPCCTL_IPCIDIE BIT(1)
52 #define IPC_DIPCCTL_IPCTBIE BIT(0)
64 #define IPC_IDCTFC_BUSY BIT(31)
71 #define IPC_IDCITC_BUSY BIT(31)
75 #define IPC_IDCIETC_DONE BIT(30)
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