Lines Matching +full:8 +full:bit
13 #define CAVS_IRQ_NUM_SHIFT 8
22 * 1. Peripheral Register bit offset.
23 * 2. CAVS logic bit offset.
64 #define DMA_HANDSHAKE_SSP3_TX 8
78 #define SSP_MN_DIV_SIZE (8)
85 #define SOC_MDIVCTRL_MCLK_OUT_EN(mclk) BIT(mclk)
97 #define SOC_NUM_CHANNELS_IN_DMAC 8
103 #define DSP_WCT_CS_TA(x) BIT(x)
104 #define DSP_WCT_CS_TT(x) BIT(4 + x)
108 /* bit field definition for LP GPDMA ownership register */
110 (BIT(15) | BIT_MASK(SOC_NUM_CHANNELS_IN_DMAC))
113 /* bit field definition for IO peripheral ownership register */
115 (BIT_MASK(SOC_NUM_I2S_INSTANCES) << 8)
116 #define SOC_DSPIOP_DMIC_OWNSEL_DSP BIT(0)
118 /* bit field definition for general ownership register */
119 #define SOC_GENO_TIMESTAMP_OWNER_DSP BIT(2)
120 #define SOC_GENO_MNDIV_OWNER_DSP BIT(1)
138 #define SOC_DMIC_SHIM_DMICLCTL_SPA BIT(0)
139 #define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
149 #define SOC_CLKCTL_REQ_FAST_CLK BIT(31)
150 #define SOC_CLKCTL_REQ_SLOW_CLK BIT(30)
151 #define SOC_CLKCTL_OCS_FAST_CLK BIT(2)
153 #define SOC_PWRCTL_DISABLE_PWR_GATING_DSP0 BIT(0)
154 #define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1)
157 uint32_t reserved[8];
196 #define SOC_GNA_POWER_CONTROL_SPA (BIT(0))
197 #define SOC_GNA_POWER_CONTROL_CPA (BIT(8))
198 #define SOC_GNA_POWER_CONTROL_CLK_EN (BIT(16))
200 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CRST BIT(1)
201 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CSTALL BIT(9)
202 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_SPA BIT(17)
203 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CPA BIT(25)