| /Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/ |
| D | renesas-ra-icu.h | 12 #define RA_ICU_PORT_IRQ0 (1 << 8)
13 #define RA_ICU_PORT_IRQ1 (2 << 8)
14 #define RA_ICU_PORT_IRQ2 (3 << 8)
15 #define RA_ICU_PORT_IRQ3 (4 << 8)
16 #define RA_ICU_PORT_IRQ4 (5 << 8)
17 #define RA_ICU_PORT_IRQ5 (6 << 8)
18 #define RA_ICU_PORT_IRQ6 (7 << 8)
19 #define RA_ICU_PORT_IRQ7 (8 << 8)
20 #define RA_ICU_PORT_IRQ8 (9 << 8)
21 #define RA_ICU_PORT_IRQ9 (10 << 8)
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| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
53 '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9',
57 '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9',
61 '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0',
64 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
65 '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0', '0', '0',
68 '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8',
69 '8', '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1',
[all …]
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| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/img/ |
| D | symbiflow.svg | 1 …8-4.9-2.3-6.4-1.5-1.5-3.6-2.3-6.4-2.3-2.4 0-4.4.7-5.9 2s-2.2 2.8-2.2 4.5c0 1.7.8 2.9 2.5 3.8 1.7.9…
|
| /Zephyr-latest/ |
| D | .editorconfig | 8 charset = utf-8
17 indent_size = 8
22 indent_size = 8
27 indent_size = 8
32 indent_size = 8
42 indent_size = 8
63 indent_size = 8
78 indent_size = 8
83 indent_size = 8
92 indent_size = 8
|
| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77951.h | 21 #define PIN_D8 RCAR_GP_PIN(0, 8)
37 #define PIN_A8 RCAR_GP_PIN(1, 8)
66 #define PIN_PWM2_A RCAR_GP_PIN(2, 8)
81 #define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8)
97 #define PIN_SD3_CMD RCAR_GP_PIN(4, 8)
115 #define PIN_RTS1 RCAR_GP_PIN(5, 8)
141 #define PIN_SSI_SCK4 RCAR_GP_PIN(6, 8)
176 #define PIN_AVB_RX_CTL RCAR_NOGP_PIN(8)
219 #define FUNC_AVB_PHY_INT IPSR(0, 8, 0)
220 #define FUNC_MSIOF2_SYNC_C IPSR(0, 8, 2)
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| D | pinctrl-r8a77961.h | 22 #define PIN_D8 RCAR_GP_PIN(0, 8)
38 #define PIN_A8 RCAR_GP_PIN(1, 8)
67 #define PIN_PWM2_A RCAR_GP_PIN(2, 8)
82 #define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8)
98 #define PIN_SD3_CMD RCAR_GP_PIN(4, 8)
116 #define PIN_RTS1 RCAR_GP_PIN(5, 8)
142 #define PIN_SSI_SCK4 RCAR_GP_PIN(6, 8)
177 #define PIN_AVB_RX_CTL RCAR_NOGP_PIN(8)
220 #define FUNC_AVB_PHY_INT IPSR(0, 8, 0)
221 #define FUNC_MSIOF2_SYNC_C IPSR(0, 8, 2)
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| /Zephyr-latest/arch/arm64/core/ |
| D | early_mem_funcs.S | 25 /* is dst pointer 8-bytes aligned? */
29 /* at least 8 bytes to set? */
30 cmp x2, #8
38 1: /* 8 bytes at a time */
39 sub x2, x2, #8
41 str x8, [x0], #8
58 /* are dst and src pointers 8-bytes aligned? */
63 /* at least 8 bytes to copy? */
64 cmp x2, #8
67 1: /* 8 bytes at a time */
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| /Zephyr-latest/samples/subsys/zbus/benchmark/ |
| D | README.rst | 23 * **CONFIG_BM_ONE_TO** number of consumers to send (1 up to 8 consumers);
52 | LIS/SUB/MSG_SUB | 1,4,8 | 2,8,32,128,512 | float | int | …
66 LISTENERS,1,8,237925.0,9253,23091
71 LISTENERS,4,8,82244.33333333333,9280,23142
75 LISTENERS,8,2,211465.66666666666,9310,23202
76 LISTENERS,8,8,56294.0,9316,23210
77 LISTENERS,8,32,15635.0,9340,23270
78 LISTENERS,8,128,5818.0,9628,23350
79 LISTENERS,8,512,4862.0,10780,23742
81 SUBSCRIBERS,1,8,1978179.3333333333,9933,23463
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| /Zephyr-latest/tests/net/traffic_class/ |
| D | testcase.yaml | 39 net.traffic_class.8:
41 - CONFIG_NET_TC_TX_COUNT=8
42 - CONFIG_NET_TC_RX_COUNT=8
68 net.traffic_class.8_no_rx:
70 - CONFIG_NET_TC_TX_COUNT=8
97 net.traffic_class.8_no_tx:
99 - CONFIG_NET_TC_RX_COUNT=8
108 - CONFIG_NET_TC_RX_COUNT=8
113 - CONFIG_NET_TC_TX_COUNT=8
129 - CONFIG_NET_TC_TX_COUNT=8
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ambiq-apollo4-pinctrl.h | 27 #define OBSBUS0_P0 APOLLO4_PINMUX(0, 8)
38 #define OBSBUS1_P1 APOLLO4_PINMUX(1, 8)
50 #define OBSBUS2_P2 APOLLO4_PINMUX(2, 8)
62 #define OBSBUS3_P3 APOLLO4_PINMUX(3, 8)
73 #define OBSBUS4_P4 APOLLO4_PINMUX(4, 8)
89 #define OBSBUS5_P5 APOLLO4_PINMUX(5, 8)
104 #define OBSBUS6_P6 APOLLO4_PINMUX(6, 8)
117 #define OBSBUS7_P7 APOLLO4_PINMUX(7, 8)
121 #define CMPRF1_P8 APOLLO4_PINMUX(8, 0)
122 #define TRIG1_P8 APOLLO4_PINMUX(8, 1)
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_nct38xx.h | 19 #define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n) * 8))
20 #define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n) * 8))
21 #define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n) * 8))
22 #define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n) * 8))
23 #define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n) * 8))
24 #define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n) * 8))
25 #define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n) * 8))
26 #define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n) * 8))
|
| /Zephyr-latest/include/zephyr/dt-bindings/reset/ |
| D | numaker_m46x_reset.h | 22 #define NUMAKER_SYS_IPRST0_CCAPRST_Pos (8)
62 #define NUMAKER_SYS_IPRST1_I2C0RST_Pos (8)
120 #define NUMAKER_SYS_IPRST2_USCI0RST_Pos (8)
160 #define NUMAKER_SYS_IPRST3_SPI5RST_Pos (8)
232 #define NUMAKER_SC0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC0RST_Pos)
233 #define NUMAKER_SC1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC1RST_Pos)
234 #define NUMAKER_SC2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC2RST_Pos)
235 #define NUMAKER_I2C4_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_I2C4RST_Pos)
236 #define NUMAKER_QSPI1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_QSPI1RST_Pos)
237 #define NUMAKER_SPI3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SPI3RST_Pos)
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/i2c/ |
| D | it8xxx2-i2c.h | 16 #define CGC_OFFSET_SMBF ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x80)
17 #define CGC_OFFSET_SMBE ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x40)
18 #define CGC_OFFSET_SMBD ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x20)
19 #define CGC_OFFSET_SMBC ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x10)
20 #define CGC_OFFSET_SMBB ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x08)
21 #define CGC_OFFSET_SMBA ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x04)
|
| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.nxp_imx_netc | 52 default 8
53 range 8 256
55 Length of the TX ring. The value must be a multiple of 8.
63 store one complete Ethernet frame, and be a multiple of 8.
74 default 8
75 range 8 256
77 Length of the RX ring. The value must be a multiple of 8.
85 store one complete Ethernet frame, and be a multiple of 8.
|
| /Zephyr-latest/soc/litex/litex_vexriscv/ |
| D | soc.h | 18 #if CONFIG_LITEX_CSR_DATA_WIDTH >= 8 in litex_read8()
21 #error CSR data width less than 8 in litex_read8()
27 #if CONFIG_LITEX_CSR_DATA_WIDTH == 8 in litex_read16()
28 return (sys_read8(addr) << 8) in litex_read16()
39 #if CONFIG_LITEX_CSR_DATA_WIDTH == 8 in litex_read32()
42 | (sys_read8(addr + 0x8) << 8) in litex_read32()
53 #if CONFIG_LITEX_CSR_DATA_WIDTH == 8 in litex_read64()
60 | ((uint64_t)sys_read8(addr + 0x18) << 8) in litex_read64()
73 #if CONFIG_LITEX_CSR_DATA_WIDTH >= 8 in litex_write8()
76 #error CSR data width less than 8 in litex_write8()
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| /Zephyr-latest/drivers/display/ |
| D | Kconfig.stm32_ltdc | 28 One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value
34 One pixel consists of 8-bit red, 8-bit green and 8-bit blue value
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_i2c_smb.h | 36 * Size 8-bit
61 * b[14:8] = Slave address 2
69 * Data register, 8-bit
85 #define MCHP_I2C_SMB_MSTR_CMD_START0 BIT(8)
97 #define MCHP_I2C_SMB_MSTR_CMD_B1_START0 BIT((8 - 8))
98 #define MCHP_I2C_SMB_MSTR_CMD_B1_STARTN BIT((9 - 8))
99 #define MCHP_I2C_SMB_MSTR_CMD_B1_STOP BIT((10 - 8))
100 #define MCHP_I2C_SMB_MSTR_CMD_B1_PEC_TERM BIT((11 - 8))
101 #define MCHP_I2C_SMB_MSTR_CMD_B1_READM BIT((12 - 8))
102 #define MCHP_I2C_SMB_MSTR_CMD_B1_READ_PEC BIT((13 - 8))
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcx-pcc.yaml | 68 8, CORE_CLK = OFMCLK / 8
79 - 8
99 8, APB1_CLK = OFMCLK / 8
110 - 8
120 - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
130 8, APB2_CLK = OFMCLK / 8
141 - 8
161 8, APB3_CLK = OFMCLK / 8
172 - 8
181 - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
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| /Zephyr-latest/drivers/pcie/endpoint/ |
| D | pcie_ep_iproc_regs.h | 117 struct paxb_imap paxb_func0_imap0[8];
118 struct paxb_imap paxb_func0_imap1[8];
120 struct paxb_imap paxb_func0_imap3[8];
121 struct paxb_imap paxb_func0_imap4[8];
215 uint32_t paxb_msg_data[8];
293 uint32_t paxb_func0_imap0[8];
294 uint32_t paxb_func1_imap0[8];
295 uint32_t paxb_func0_imap0_upper[8];
296 uint32_t paxb_func1_imap0_upper[8];
316 struct paxb_64 paxb_func0_imap1[8];
[all …]
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| /Zephyr-latest/drivers/crypto/ |
| D | crypto_intel_sha_priv.h | 26 #define SHA1_ALGORITHM_HASH_SIZEOF (160 / 8)
27 #define SHA224_ALGORITHM_HASH_SIZEOF (224 / 8)
28 #define SHA256_ALGORITHM_HASH_SIZEOF (256 / 8)
29 #define SHA384_ALGORITHM_HASH_SIZEOF (384 / 8)
30 #define SHA512_ALGORITHM_HASH_SIZEOF (512 / 8)
32 #define SHA_MAX_SESSIONS 8
35 (((x >> 24) & 0x000000FF) | ((x << 24) & 0xFF000000) | ((x >> 8) & 0x0000FF00) | \
36 ((x << 8) & 0x00FF0000))
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| /Zephyr-latest/soc/intel/alder_lake/ |
| D | soc_gpio.h | 36 (pin_offset % 8) ? \
38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
42 #define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
|
| /Zephyr-latest/soc/intel/elkhart_lake/ |
| D | soc_gpio.h | 36 (pin_offset % 8) ? \
38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
42 #define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,stm32-qdec.yaml | 62 3: Fs = F_clk, N=8
64 5: Fs = F_clk/2, N=8
66 7: Fs = F_clk/4, N=8
67 8: Fs = F_clk/8, N=6
68 9: Fs = F_clk/8, N=8
71 12: Fs = F_clk/16, N=8
74 15: Fs = F_clk/32, N=8
86 - 8 # FDIV8_N6
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| /Zephyr-latest/subsys/fb/ |
| D | cfb.c | 20 #define MSB_BIT_MASK(x) (BIT_MASK(x) << (8 - x))
52 /** Number of pixels per tile, typically 8 */
74 (fptr->width * fptr->height / 8U); in get_glyph_ptr()
81 return glyph_ptr[x * (fptr->height / 8U) + y]; in get_glyph_byte()
92 * a byte is interpreted as 8 pixels ordered vertically among each other.
119 * by separating per 8-line boundaries. in draw_char_vtmono()
123 const size_t fb_index = (fb_y / 8U) * fb->x_res + fb_x; in draw_char_vtmono()
124 const size_t offset = y % 8; in draw_char_vtmono()
125 const uint8_t bottom_lines = ((offset + fptr->height) % 8); in draw_char_vtmono()
143 next_byte = get_glyph_byte(glyph_ptr, fptr, g_x, g_y / 8); in draw_char_vtmono()
[all …]
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| /Zephyr-latest/tests/kernel/common/src/ |
| D | pow2.c | 35 char static_array8[Z_POW2_CEIL(8)];
42 BUILD_ASSERT(sizeof(static_array5) == 8);
43 BUILD_ASSERT(sizeof(static_array7) == 8);
44 BUILD_ASSERT(sizeof(static_array8) == 8);
73 test_pow2_ceil_x(5, 8); in ZTEST()
74 test_pow2_ceil_x(7, 8); in ZTEST()
75 test_pow2_ceil_x(8, 8); in ZTEST()
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