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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_i2c_smb.h4 * SPDX-License-Identifier: Apache-2.0
36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
47 /* Status Read-only */
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
[all …]
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
16 #define MCHP_FIRST_GIRQ_NOS 8u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
35 /* MEC172x implements 8 priority levels. ARM NVIC 0 = highest priority */
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Dmec172x_pcr.h4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
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Dmec172x_espi_vw.h4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
28 /* 32-bit word 1 (bits[63:32]) */
33 #define ESPI_M2SW1_SRC1_SEL_POS 8
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
43 /* 32-bit word 2 (bits[95:64]) */
[all …]
Dmec172x_p80bd.h4 * SPDX-License-Identifier: Apache-2.0
15 /* HDATA - Write-Only 32-bit */
20 * EC-only Data/Attributes 16-bit
22 * b[15:8] = data attributes
27 #define MCHP_P80BD_ECDA_APOS 8
30 #define MCHP_P80BD_ECDA_LANE_POS 8
42 #define MCHP_P80BD_ECDA_NE BIT(12)
43 #define MCHP_P80BD_ECDA_OVR BIT(13)
44 #define MCHP_P80BD_ECDA_THR BIT(14)
49 #define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */
[all …]
/Zephyr-latest/drivers/display/
DKconfig.stm32_ltdc3 # Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
4 # SPDX-License-Identifier: Apache-2.0
7 bool "STM32 LCD-TFT display controller driver"
14 Enable driver for STM32 LCT-TFT display controller periheral.
23 Specify the color pixel format for the STM32 LCD-TFT display controller.
28 One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value
34 One pixel consists of 8-bit red, 8-bit green and 8-bit blue value
40 One pixel consists of 5-bit red, 6-bit green and 5-bit blue value
51 - 0 frame buffer maintained by application, must write with full screen pixels.
52 - 1 single frame buffer in stm32 ltdc driver.
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/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
34 #define RDR_MASK_RDAT GENMASK(8, 0)
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
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/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
18 ((flag_u32) >> ROUND_DOWN(LOG2((flag_u32)), 8))
28 #define MCP251XFD_TEF_FIFO_ITEM_SIZE 8
29 #define MCP251XFD_TX_QUEUE_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
32 #define MCP251XFD_RX_FIFO_ITEM_SIZE (4 + 8 + MCP251XFD_PAYLOAD_SIZE)
34 #define MCP251XFD_RX_FIFO_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
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/Zephyr-latest/drivers/spi/
Dspi_pw.h1 /* spi_pw.h - Penwell SPI driver definitions */
6 * SPDX-License-Identifier: Apache-2.0
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
59 /* SSP Baud rate sscr0[19:8] */
66 /* [19:8] 12 bits */
67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
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Dspi_andes_atcspi200.h4 * SPDX-License-Identifier: Apache-2.0
42 #define TFMAT_DATA_LEN_OFFSET (8)
44 #define TFMAT_CPHA_MSK BIT(0)
45 #define TFMAT_CPOL_MSK BIT(1)
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_LSB_MSK BIT(3)
48 #define TFMAT_DATA_MERGE_MSK BIT(7)
49 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
66 #define IEN_RX_FIFO_MSK BIT(2)
67 #define IEN_TX_FIFO_MSK BIT(3)
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Dspi_dw.h1 /* spi_dw.h - Designware SPI driver private definitions */
7 * SPDX-License-Identifier: Apache-2.0
26 typedef void (*spi_dw_set_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
27 typedef void (*spi_dw_clear_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
28 typedef int (*spi_dw_test_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
79 static void aux_reg_set_bit(uint8_t bit, mm_reg_t addr, uint32_t off) in aux_reg_set_bit() argument
81 sys_io_set_bit(addr + off/4, bit); in aux_reg_set_bit()
84 static void aux_reg_clear_bit(uint8_t bit, mm_reg_t addr, uint32_t off) in aux_reg_clear_bit() argument
86 sys_io_clear_bit(addr + off/4, bit); in aux_reg_clear_bit()
89 static int aux_reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off) in aux_reg_test_bit() argument
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/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
40 IPC_EVENT_BIT(8) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
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/Zephyr-latest/drivers/ethernet/
Deth_enc424j600_priv.h1 /* ENC424J600 Stand-alone Ethernet Controller with SPI
6 * SPDX-License-Identifier: Apache-2.0
136 #define ENC424J600_PSFR_PHCON1 (BIT(8) | 0x00)
137 #define ENC424J600_PSFR_PHSTAT1 (BIT(8) | 0x01)
138 #define ENC424J600_PSFR_PHANA (BIT(8) | 0x04)
139 #define ENC424J600_PSFR_PHANLPA (BIT(8) | 0x05)
140 #define ENC424J600_PSFR_PHANE (BIT(8) | 0x06)
141 #define ENC424J600_PSFR_PHCON2 (BIT(8) | 0x11)
142 #define ENC424J600_PSFR_PHSTAT2 (BIT(8) | 0x1B)
143 #define ENC424J600_PSFR_PHSTAT3 (BIT(8) | 0x1F)
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Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
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/Zephyr-latest/subsys/fs/ext2/
Dext2_bitmap.c4 * SPDX-License-Identifier: Apache-2.0
20 LOG_DBG("Setting %d bit in bitmap", index); in ext2_bitmap_set()
22 uint32_t idx = index / 8; in ext2_bitmap_set()
23 uint32_t off = index % 8; in ext2_bitmap_set()
27 return -EINVAL; in ext2_bitmap_set()
30 __ASSERT((bm[idx] & BIT(off)) == 0, "Bit %d set in bitmap", index); in ext2_bitmap_set()
33 bm[idx] |= BIT(off); in ext2_bitmap_set()
41 LOG_DBG("Unsetting %d bit in bitmap", index); in ext2_bitmap_unset()
43 uint32_t idx = index / 8; in ext2_bitmap_unset()
44 uint32_t off = index % 8; in ext2_bitmap_unset()
[all …]
/Zephyr-latest/dts/riscv/ite/
Dit82xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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/Zephyr-latest/drivers/sdhc/
Drcar_mmc_registers.h4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/sys/util_macro.h> /* for BIT macro */
16 #define RCAR_MMC_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
17 #define RCAR_MMC_CMD_MULTI BIT(13) /* multiple block transfer */
18 #define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */
19 #define RCAR_MMC_CMD_DATA BIT(11) /* data transfer */
20 #define RCAR_MMC_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
22 #define RCAR_MMC_CMD_RSP_NONE (3 << 8) /* response: none */
23 #define RCAR_MMC_CMD_RSP_R1 (4 << 8) /* response: R1, R5, R6, R7 */
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
39 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
[all …]
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
40 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
24 #define I2SIPCMC 8
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
47 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
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/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/modules/lvgl/
Dlvgl_display_mono.c4 * SPDX-License-Identifier: Apache-2.0
18 uint8_t bit; in set_px_at_pos() local
21 if (caps->screen_info & SCREEN_INFO_MONO_VTILED) { in set_px_at_pos()
22 buf = dst_buf + x + y / 8 * width; in set_px_at_pos()
24 if (caps->screen_info & SCREEN_INFO_MONO_MSB_FIRST) { in set_px_at_pos()
25 bit = 7 - y % 8; in set_px_at_pos()
27 bit = y % 8; in set_px_at_pos()
30 buf = dst_buf + x / 8 + y * width / 8; in set_px_at_pos()
32 if (caps->screen_info & SCREEN_INFO_MONO_MSB_FIRST) { in set_px_at_pos()
33 bit = 7 - x % 8; in set_px_at_pos()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpmc_interface.h2 * SPDX-License-Identifier: Apache-2.0
18 * The requesting agent will write the PMC command op-code into this field.
29 * Some commands require additional information which is passed into this 8 bit field.
31 #define CW_PMC_IPC_PARAM1 GENMASK(15, 8)
34 * Some commands require additional information which is passed into this 8 bit field.
39 * Some commands require additional information which is passed into this 4 bit field.
49 * busy - The run/busy bit can only be set by the requesting agent and can only be cleared by the
50 * responding agent. When this bit is set it will prompt the PMC to execute the command placed in
55 #define CW_PMC_IPC_BUSY BIT(31)
61 * No operation - PMC FW will clear the run / busy bit and return a success response
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/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h6 * Copyright (c) 2015-2016, Intel Corporation.
8 * SPDX-License-Identifier: Apache-2.0
19 #define BSWAP_16(x) ((uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)))
24 (((x) >> 8) & 0xff00) | \
25 (((x) & 0xff00) << 8) | \
34 (((x) >> 8) & 0xff0000) | \
35 (((x) & 0xff0000) << 8) | \
41 (((x) >> 8) & 0xff000000) | \
42 (((x) & 0xff000000) << 8) | \
48 * @brief Convert 16-bit integer from little-endian to host endianness.
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