Searched +full:75 +full:mhz (Results 1 – 10 of 10) sorted by relevance
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,imx8m-pinctrl.yaml | 77 - "75-ohm"
90 011 75_OHM — 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
91 100 85_OHM — 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
|
| /Zephyr-latest/soc/snps/arc_iot/ |
| D | sysconf.c | 11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
[all …]
|
| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 41 …es 2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100MHz, 0 degrees phase of…
51 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
60 .duty = 75,
125 [00:00:00.670,000] <inf> CLK_CTRL_LITEX: CLKOUT1: set duty: 75%
129 CLKOUT1: get_status: rate:15000000 phase:0 duty:75
|
| /Zephyr-latest/boards/shields/weact_ov2640_cam_module/boards/ |
| D | mini_stm32h743.overlay | 8 * The OV2640 PCLK is around 72 MHz for QQVGA resolution (160x120) with MCO1_SEL_HSI48
48 dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
|
| /Zephyr-latest/drivers/audio/ |
| D | tlv320dac310x.h | 33 #define DAC_PROC_CLK_FREQ_MAX 49152000 /* 49.152 MHz */
41 #define DAC_MOD_CLK_FREQ_MIN 2800000 /* 2.8 MHz */
42 #define DAC_MOD_CLK_FREQ_MAX 6200000 /* 6.2 MHz */
87 #define BEEP_LEN_LSB_ADDR (struct reg_addr){0, 75}
|
| /Zephyr-latest/boards/st/stm32wb5mmg/doc/ |
| D | stm32wb5mmg.rst | 19 - Frequency band 2402-2480 MHz
23 - Range: up to 75 meters
25 …ed Arm|reg| Cortex|reg|-M4 CPU with FPU and ART (adaptive real-time accelerator) up to 64 MHz speed
27 - Fully integrated BOM, including 32 MHz radio and 32 kHz RTC crystals
49 - Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 64 MHz
77 - 32 MHz crystal oscillator with integrated
83 - Internal multispeed 100 kHz to 48 MHz
86 - High speed internal 16 MHz factory
209 as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
|
| /Zephyr-latest/dts/arm/atmel/ |
| D | samd5x.dtsi | 231 interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
321 * 16 MHz max, source clock must not exceed 100 MHz.
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
343 * 16 MHz max, source clock must not exceed 100 MHz.
346 * -> 48 MHz GCLK(2) / 4 = 12 MHz
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | lpm_rt1064.c | 228 /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */ in clock_full_power()
250 /* Switch to 24MHz core clock, so ARM PLL can power down */ in clock_low_power()
254 /* Switch peripheral mux to 24MHz source */ in clock_low_power()
271 /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */ in clock_low_power()
452 /* The target full power frequency for the flexspi clock is ~100MHz. in imxrt_lpm_init()
|
| /Zephyr-latest/drivers/ethernet/ |
| D | eth_sam_gmac.c | 835 * According to 802.3 MDC should be less then 2.5 MHz.
1106 eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 1, 75); in gmac_init()
1108 /* For multiple priority queues, 802.1Qav suggests using 75% for the in gmac_init()
1116 * 75%, but split the bandwidth between them manually. in gmac_init()
|
| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_kw41z.c | 1021 /* Set CCA threshold to -75 dBm */ in kw41z_init()
1042 /* Set default channel to 2405 MHZ */ in kw41z_init()
|
