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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx7d-pinctrl.yaml81 default: "100k"
84 - "5k"
85 - "47k"
86 - "100k"
89 Default of 100k as this is most common default register value for
91 01: 5K- 5K pull up resistor
92 10: 47K- 47K pull up resistor
93 11: 100K- 100K pull up resistor
Dnxp,mcux-rt-pinctrl.yaml85 - "r0-5"
103 default: "47k"
106 - "47k"
107 - "100k"
108 - "22k"
112 47k resistor selected as default due to this being the default pullup
115 01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
116 10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
117 11 PUS_2_22K_Ohm_Pull_Up — 22K Ohm Pull Up
121 default: "100k"
[all …]
/Zephyr-latest/samples/modules/tflite-micro/magic_wand/train/
Ddata_augmentation.py36 for k in range(denominator):
38 k][j] = (data[molecule * i + k][j] * (denominator - k) +
39 data[molecule * i + k + 1][j] * k) / denominator
52 for num in range(5): # pylint: disable=unused-variable
58 for num in range(5):
61 tmp_data[i][j] = data[i][j] + 5 * random.random()
65 fractions = [(3, 2), (5, 3), (2, 3), (3, 4), (9, 5), (6, 5), (4, 5)]
/Zephyr-latest/lib/hash/
Dhash_func32_murmur3.c10 static inline uint32_t murmur_32_scramble(uint32_t k) in murmur_32_scramble() argument
12 k *= 0xcc9e2d51; in murmur_32_scramble()
13 k = (k << 15) | (k >> 17); in murmur_32_scramble()
14 k *= 0x1b873593; in murmur_32_scramble()
16 return k; in murmur_32_scramble()
21 uint32_t k; in sys_hash32_murmur3() local
27 k = *(const uint32_t *)str; in sys_hash32_murmur3()
28 h ^= murmur_32_scramble(k); in sys_hash32_murmur3()
30 h = h * 5 + 0xe6546b64; in sys_hash32_murmur3()
33 for (k = 0; n != 0; --n, ++str) { in sys_hash32_murmur3()
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_vbat.h22 #define MCHP_VBATR_PFRS_WDT_POS 5u
29 #define MCHP_VBATR_PFRS_WDT BIT(5)
33 /* Offset 0x08 32K Clock Source register */
64 /* 32K silicon OSC when chip powered by VBAT or VTR */
66 /* 32K external crystal when chip powered by VBAT or VTR */
68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
70 /* 32K input pin on VTR. Switch to crystal on VBAT */
72 /* Disable internal 32K VBAT clock source when VTR is off */
97 uint32_t RSVD2[5];
/Zephyr-latest/dts/bindings/pwm/
Dtelink,b91-pwm.yaml19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
23 description: Enable 32K Source Clock for PWM Channel 0
27 description: Enable 32K Source Clock for PWM Channel 1
31 description: Enable 32K Source Clock for PWM Channel 2
35 description: Enable 32K Source Clock for PWM Channel 3
39 description: Enable 32K Source Clock for PWM Channel 4
43 description: Enable 32K Source Clock for PWM Channel 5
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi39 drive-strength = "r0-5";
41 bias-pull-up-value = "100k";
57 drive-strength = "r0-5";
59 bias-pull-up-value = "100k";
65 drive-strength = "r0-5";
67 bias-pull-up-value = "100k";
73 drive-strength = "r0-5";
75 bias-pull-up-value = "100k";
148 bias-pull-up-value = "100k";
177 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi40 drive-strength = "r0-5";
42 bias-pull-up-value = "100k";
58 drive-strength = "r0-5";
60 bias-pull-up-value = "100k";
66 drive-strength = "r0-5";
68 bias-pull-up-value = "100k";
74 drive-strength = "r0-5";
76 bias-pull-up-value = "100k";
149 bias-pull-up-value = "100k";
178 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v2_internal.h13 * The size of the region is a 5-bit field, the three MSB bits are
18 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
19 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
20 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
45 #define ARC_FEATURE_MPU_ALIGNMENT_BITS 5
Darc_mpu_v6_internal.h16 * The size of the region is a 5-bit field, the three MSB bits are
21 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
22 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
23 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
59 #define ARC_FEATURE_MPU_ALIGNMENT_BITS 5
/Zephyr-latest/drivers/dma/
Ddma_iproc_pax_v1.h22 #define RM_COMM_CONTROL_AE_TIMEOUT_EN_SHIFT 5
23 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
36 /* ascii signature 'V' 'K' */
51 * Per-ring memory, with 8K & 4K alignment
53 * s/w need to allocate extra upto 8K to
65 uint64_t bdcount : 5; /*bdcount 40:36*/
Ddma_iproc_pax_v2.h25 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
53 * to make sure BD memories fall in 4K alignment.
58 * Per-ring memory, with 8K & 4K alignment
60 * s/w need to allocate extra upto 8K to
73 uint64_t bdcount : 5; /*bdcount 36:40*/
/Zephyr-latest/tests/lib/lockfree/src/
Dtest_spsc.c90 for (int k = 0; k < 3; k++) { in ZTEST() local
94 zassert_equal(*entry, i * 3 + k, "Consume value should equal i*3+k"); in ZTEST()
125 for (int k = 0; k < 3; k++) { in ZTEST() local
129 zassert_equal(*entry, k, "Consume value should equal i*3+k"); in ZTEST()
136 #define MAX_RETRIES 5
218 K_PRIO_PREEMPT(5), in ZTEST()
224 K_PRIO_PREEMPT(5), in ZTEST()
/Zephyr-latest/boards/shields/x_nucleo_eeprma2/
Dx_nucleo_eeprma2.overlay28 timeout = <5>;
41 timeout = <5>;
54 timeout = <5>;
70 * All chip select pins have an on board 10k pull-up resistor to VCC,
74 * All hold pins are connected to VCC with a 10k pull-up, and
77 * All write-protect pins are connected to J11 with a 10k pull-up
91 timeout = <5>;
105 timeout = <5>;
118 /* max-frequency 10MHz for vcc>=2.5V and 5MHz for vcc>=1.8V */
120 timeout = <5>;
/Zephyr-latest/samples/drivers/lcd_cyclonev_socdk/src/
Dcommands.h34 * Bit 7 6 5 4 3 2 1 0 Hex
56 * 5 14400
57 * 6 19.2K
58 * 7 57.6K
59 * 8 115.2K
/Zephyr-latest/dts/bindings/clock/
Dst,stm32wb-rcc.yaml24 - 5
55 (A.K.A C2HPRE)
73 (A.K.A SHDHPRE)
/Zephyr-latest/boards/snps/nsim/arc_classic/support/
Dmdb_hs6x.args25 -bpu_tosq_entries=5
28 -smart_version=5
34 -mmu_pgsz=4K
41 -dcache_version=5
Dnsim_hs6x.props31 nsim_bpu_tosq_entries=5
34 nsim_isa_smart_version=5
41 mmu_pagesize=4K
48 nsim_isa_dc_version=5
Dmdb_hs6x_smp.args25 -bpu_tosq_entries=5
28 -smart_version=5
34 -mmu_pgsz=4K
41 -dcache_version=5
Dmdb_hs6x_smp_12cores.args23 -bpu_tosq_entries=5
26 -smart_version=5
32 -mmu_pgsz=4K
39 -dcache_version=5
/Zephyr-latest/samples/drivers/led/xec/
DREADME.rst42 - Make sure there are no jumpers on JP54 1-2 and JP21 4-5
49 - Connect GPIO 0153 to board LED7 by placing a wire from JP71-5 to JP146-5.
51 JP146-5 is connected to MEC172x VCI_OUT1 without a jumper. Force VCI_OUT1
53 to the VBAT rail via a 100K pull-up. Requires VBAT power rail is connected
61 high by forcing VCI_IN2 high: install a jumper on J55 5-6 which pulls VCI_IN2
62 to the VBAT rail via a 100K pull-up. Requires VBAT power rail is connected
/Zephyr-latest/tests/drivers/w1/w1_api/boards/
Dnucleo_g0b1re.overlay11 * with approximately R=5k resistance is suggested.
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi29 bias-pull-down-value = "100k";
40 drive-strength = "r0-5";
41 bias-pull-up-value = "100k";
47 bias-pull-down-value = "100k";
48 drive-strength = "r0-5";
54 drive-strength = "r0-5";
56 bias-pull-up-value = "100k";
179 bias-pull-up-value = "47k";
191 bias-pull-down-value = "100k";
275 bias-pull-up-value = "47k";
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc54xxx.dtsi53 * (note: reference manual says "up to <n>K")
56 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K
57 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000
58 * LPC5411x: RAMX: 32K, SRAM0: 64K, SRAM1: 64K, SRAM2: 32K
83 * LPC54018: 192K @ 0x04000000
84 * LPC540xx: 192K @ 0x04000000
85 * LPC541xx: 32K @ 0x04000000
146 interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
/Zephyr-latest/boards/st/stm32l1_disco/doc/
Dindex.rst16 - STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM, 4K EEPROM
17 - STM32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM, 8K EEPROM
33 - Board power supply: through USB bus or from an external 5 V supply voltage
34 - External application power supply: 3 V and 5 V

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