Searched full:57 (Results 1 – 25 of 208) sorted by relevance
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8 /* request 57 for XSPI1 */9 dmas = <&gpdma1 4 57 STM32_DMA_PERIPH_TX10 &gpdma1 5 57 STM32_DMA_PERIPH_RX>;
9 default 57
10 default 57
8 max30101@57 {
12 i2c_eeprom: eeprom@57 {
19 interrupts = <56 0 57 0 58 0 59 0 60 0 97 0>;
25 ti_ccfg_partition: partition@57fa8 {
73 54, /* 57 - BIDIRECTIONAL */76 57, /* 60 - BIDIRECTIONAL */
37 /* configure pin 57 as UART0 RX and pin 62 as UART0 RTS */39 /* both pin 57 and 62 have pull-up enabled */
26 interrupts = <56 0 57 0 58 0 59 0 60 0>;
33 interrupts = <56 0 57 0 58 0 59 0 60 0>;
27 interrupts = <56 0 57 0 58 0 59 0 60 0>;
176 #define GPIO2_P57 TI_CC32XX_PINMUX(57U, 0U)177 #define UART0_RX_P57 TI_CC32XX_PINMUX(57U, 3U)178 #define UART1_RX_P57 TI_CC32XX_PINMUX(57U, 6U)179 #define GT_CCP02_P57 TI_CC32XX_PINMUX(57U, 7U)
18 interrupts = <56 0 57 0 58 0 59 0 60 0>;
34 eeprom0_lmp90100_evb: eeprom@57 {
22 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
67 57 RESET_OUT_N SLEEP_N 64
37 57 RESET - (58)
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
34 dma-requests= <57>;
67 #define CORE0_DRAM0_PMS_INTR_SOURCE 57
48 55 3 56 3 57 3 58 3 /* PINS 4:7 */
