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/Zephyr-latest/soc/espressif/esp32s3/
DKconfig24 If you use 16KB instruction cache rather than 32KB instruction cache,
25 then the other 16KB will be managed by heap allocator.
28 bool "16KB"
30 bool "32KB"
45 bool "4 ways"
52 default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
85 If you use 32KB data cache rather than 64KB data cache,
86 the other 32KB will be added to the heap.
89 bool "16KB"
91 bool "32KB"
[all …]
/Zephyr-latest/drivers/flash/
Dflash_gd32_v3.c25 {.pages_count = 4, .pages_size = KB(16)},
26 {.pages_count = 1, .pages_size = KB(64)},
27 {.pages_count = 3, .pages_size = KB(128)},
31 {.pages_count = 4, .pages_size = KB(16)},
32 {.pages_count = 1, .pages_size = KB(64)},
33 {.pages_count = 7, .pages_size = KB(128)},
37 {.pages_count = 4, .pages_size = KB(16)},
38 {.pages_count = 1, .pages_size = KB(64)},
39 {.pages_count = 7, .pages_size = KB(128)},
40 {.pages_count = 4, .pages_size = KB(16)},
[all …]
Dflash_stm32f7x.c94 sector += 4U; in erase_sector()
228 /* RM0385, table 4: STM32F750xx */
229 {.pages_count = 2, .pages_size = KB(32)},
231 #elif FLASH_SECTOR_TOTAL == 4
233 /* RM0431, table 4: STM32F730xx */
234 {.pages_count = 4, .pages_size = KB(16)},
240 {.pages_count = 4, .pages_size = KB(16)},
241 {.pages_count = 1, .pages_size = KB(64)},
242 {.pages_count = 3, .pages_size = KB(128)},
247 {.pages_count = 4, .pages_size = KB(32)},
[all …]
Dflash_stm32f4x.c26 #elif FLASH_STM32_WRITE_BLOCK_SIZE == 4
167 sector += 4U; in erase_sector()
328 * sectors (16 KB) in the second bank occurring after the large ones
329 * (128 KB) in the first. We could consider supporting this as two
338 {.pages_count = 4, .pages_size = KB(16)},
339 {.pages_count = 1, .pages_size = KB(64)},
344 {.pages_count = 4, .pages_size = KB(16)},
345 {.pages_count = 1, .pages_size = KB(64)},
346 {.pages_count = 1, .pages_size = KB(128)},
352 * RM0383, table 4: STM32F411xE
[all …]
/Zephyr-latest/tests/drivers/flash/common/boards/
Dgd32a503v_eval.overlay13 /* Set 4KB of storage at the border of bank0(256KB) and bank1(128KB). */
16 reg = <0x0003f800 DT_SIZE_K(4)>;
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts103 * Total size : 256 KB
104 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors,
115 * Total size : 128 KB
116 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
126 * Total size : 64 KB
127 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
138 reg = <0x00000000 DT_SIZE_K(4)>;
159 * hardware blinking is 250ms (i.e. "error" fast blink at 4 Hz).
176 * So any prescaler value above 182 is good for a 4 Hz hardware
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
29 * 0x80100000..0x80101000 (the first 4k block of RAM).
66 volatile struct scar_reg *scar_regs[CONFIG_ILM_MAX_SIZE / 4];
129 "ILM physical base address (%p) must be 4k-aligned", __ilm_ram_start); in it8xxx2_ilm_init()
131 "ILM flash base address (%p) must be 4k-aligned", __ilm_flash_start); in it8xxx2_ilm_init()
162 /* SCAR0 SRAM 4KB */
167 SCAR_REG(4),
180 * maximum ILM size are 60KB, the ILM size of other varients
184 /* SCAR15 SRAM 4KB */
186 /* SCAR16 SRAM 16KB */
[all …]
/Zephyr-latest/soc/espressif/esp32c3/
DKconfig27 can free up to 35kB of RAM.
36 by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
37 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
/Zephyr-latest/boards/seagate/faze/support/
Dopenocd.cfg5 # An external debug probe must be connected to the SWD port (4-pins J2 header).
10 # NXP LPC11U24 Cortex-M0 with 128KB Flash and 20KB + 4KB SRAM
/Zephyr-latest/soc/espressif/esp32c2/
DKconfig24 by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
25 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
/Zephyr-latest/soc/espressif/esp32c6/
DKconfig27 by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
28 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
/Zephyr-latest/samples/basic/minimal/
DREADME.rst29 * Reference ROM size: 7-8KB
42 * Reference ROM size: 7-8KB
55 * Reference ROM size: 3-4KB
68 * Reference ROM size: 4-5KB
81 * Reference ROM size: 2-3KB
/Zephyr-latest/boards/silabs/radio_boards/slwrb4250b/
Dslwrb4250b.dts38 pin-location = <GECKO_LOCATION(28) GECKO_PORT_F GECKO_PIN(4)>;
49 /* Reserve 32 kB for the bootloader */
56 /* Reserve 94 kB for the application in slot 0 */
62 /* Reserve 94 kB for the application in slot 1 */
68 /* Reserve 30 kB for the scratch partition */
74 /* Set 6Kb of storage at the end of the 256Kb of flash */
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l233rc.dtsi38 * From other GD32 DataSheets, we can find 1KB page normally have a
41 * time to 4 times of 1KB page.
44 page-size = <DT_SIZE_K(4)>;
/Zephyr-latest/boards/st/stm32l562e_dk/
Dstm32l562e_dk_stm32l562xx_ns.dts56 /* 4KB at the end of 512KB flash is set for storage */
58 reg = <0x0007f000 DT_SIZE_K(4)>;
/Zephyr-latest/tests/drivers/wifi/nrf_wifi/
Dprj.conf35 CONFIG_NRF70_MAX_TX_AGGREGATION=4
36 # nRF70 is main consumer: (16 + 8) * 1600 = ~40KB + ~40KB control path (experimental)
41 CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=4
/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu.c5 * table format. The standard page size is 4 kB, 1 MB sections
41 l1_page_table __aligned(KB(16)) = {0};
43 * Array of level 2 page tables with 4k granularity:
48 l2_page_tables[CONFIG_ARM_MMU_NUM_L2_TABLES] __aligned(KB(1)) = {0};
53 * each mapping a 4 kB page, it currently contains.
394 * down into 4k segments using a L2 table with identical attributes
445 * entry has to be broken down to the full 256 4k-wide entries of a
447 * modification of the subset can be performed with a 4k granularity.
459 * be converted from L1 1 MB section mapping to L2 4 kB page
530 rem_size -= KB(4); in arm_mmu_remap_l1_section_to_l2_table()
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso11u68/support/
Dopenocd.cfg15 # NXP LPC11U68 Cortex-M0 with 256kB flash and 32kB + 4kB SRAM.
/Zephyr-latest/dts/bindings/espi/
Dnuvoton,npcx-espi-taf.yaml37 Erase block size of target flash. The default was 4KB Erase Block Size.
38 All Intel platforms require support for at least 4 KB Erase Block Size.
/Zephyr-latest/boards/silabs/starter_kits/slstk3400a/
Dslstk3400a.dts33 gpios = <&gpiof 4 0>;
84 location-rx = <GECKO_LOCATION(4) GECKO_PORT_A GECKO_PIN(0)>;
85 location-tx = <GECKO_LOCATION(4) GECKO_PORT_F GECKO_PIN(2)>;
96 /* Set 4Kb of storage at the end of the 64Kb of flash */
/Zephyr-latest/include/zephyr/arch/arm/mpu/
Darm_mpu_v7m.h88 #define REGION_1K REGION_SIZE(1KB)
89 #define REGION_2K REGION_SIZE(2KB)
90 #define REGION_4K REGION_SIZE(4KB)
91 #define REGION_8K REGION_SIZE(8KB)
92 #define REGION_16K REGION_SIZE(16KB)
93 #define REGION_32K REGION_SIZE(32KB)
94 #define REGION_64K REGION_SIZE(64KB)
95 #define REGION_128K REGION_SIZE(128KB)
96 #define REGION_256K REGION_SIZE(256KB)
97 #define REGION_512K REGION_SIZE(512KB)
[all …]
/Zephyr-latest/samples/drivers/virtualization/ivshmem/doorbell/boards/
Dqemu_x86_64.conf2 # This is enough memory for a 4KB ivshmem shared memory
/Zephyr-latest/dts/arm/ti/
Dam64x_m4.dtsi28 reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */
33 reg = <0x40000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */
48 uart0: serial@4a00000 {
51 interrupts = <24 4>;
59 uart1: serial@4a10000 {
62 interrupts = <25 4>;
/Zephyr-latest/samples/boards/nordic/system_off/boards/
Dnrf54l15dk_nrf54l05_cpuapp.overlay4 reg = <0x20017000 DT_SIZE_K(4)>;
21 * 96 - 4 = 92KB = 0x17000
Dnrf54l15dk_nrf54l10_cpuapp.overlay4 reg = <0x2002f000 DT_SIZE_K(4)>;
21 * 192 - 4 = 188KB = 0x2f000

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