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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-rp2350b-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "rpi-pico-rp2350-pinctrl-common.h"
12 /* RP2350B is in a QFN-80 package, and extends the set of available pins
22 #define SPI0_CSN_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_SPI)
25 #define SPI1_RX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_SPI)
41 #define UART0_RX_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_UART)
44 #define UART0_TX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_UART)
60 #define I2C0_SCL_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_I2C)
63 #define I2C0_SDA_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_I2C)
79 #define PWM_10B_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PWM)
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Desp32s2-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
113 ESP32_PINMUX(37, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
122 ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
240 ESP32_PINMUX(37, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
249 ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
367 ESP32_PINMUX(37, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
376 ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
494 ESP32_PINMUX(37, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
503 ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
621 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
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Desp32s3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
79 #define I2C0_SCL_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
85 #define I2C0_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
170 #define I2C0_SDA_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
176 #define I2C0_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
261 #define I2C1_SCL_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
267 #define I2C1_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
352 #define I2C1_SDA_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
358 #define I2C1_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
443 #define I2S0_I_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
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Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
48 #define SMARTBOND_FUNC_PORT0_DCF 37
51 #define SMARTBOND_FUNC_PORT3_DCF 40
Dambiq-apollo3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
275 #define TRIG2_P37 APOLLO3_PINMUX(37, 0)
276 #define NCE37_P37 APOLLO3_PINMUX(37, 1)
277 #define UA0RTS_P37 APOLLO3_PINMUX(37, 2)
278 #define GPIO_P37 APOLLO3_PINMUX(37, 3)
279 #define SCCIO_P37 APOLLO3_PINMUX(37, 4)
280 #define UART1TX_P37 APOLLO3_PINMUX(37, 5)
281 #define PDMCLK_P37 APOLLO3_PINMUX(37, 6)
282 #define CTIM29_P37 APOLLO3_PINMUX(37, 7)
295 #define UART0RX_P40 APOLLO3_PINMUX(40, 0)
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Dsi32-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
60 #define SI32_SIGNAL_TIMER0_EX 37
65 #define SI32_SIGNAL_UART0_TX 40
/Zephyr-latest/dts/bindings/gpio/
Dti,boosterpack-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
15 through 40. The BoosterPack pinout is depicted below:
17 1 3.3V 21 5V 40 GPIO 20 GND
20 4 UART TXD 24 Analog 37 GPIO 17 GPIO
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
Dnxp,parallel-lcd-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,parallel-lcd-connector"
9 exposed on a 40 pin flexible printed cable connector. The pins have the
17 5-7 GND
18 8-12 LCD D11-D15
19 13-14 GND
20 15-20 LCD D5-D10
21 21-23 GND
22 24-28 LCD D0-D4
31 37-40 NC
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Dnxp,cam-44pins-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on NXP 44-pin board-to-board camera connector.
27 38 DOVDD D0 37
28 40 DGND DGND 39
31 compatible: "nxp,cam-44pins-connector"
33 include: [gpio-nexus.yaml, base.yaml]
Dadi,sdp-120.yaml4 # SPDX-License-Identifier: Apache-2.0
9 120-pin SDP interface:
47 37 SPI_SEL_B_N SPI_MOSI 84
50 40 GND GND 81
72 compatible: "adi,sdp-120"
74 include: [gpio-nexus.yaml, base.yaml]
Dst,dsi-lcd-qsh-030.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on QSH-030-01-F-D-A connector used as DSI LCD connector.
9 (1) GND - (2)
11 (5) DSI_CK_N - (6)
12 (7) GND - (8)
13 (9) DSI_D0_P - (10)
14 (11) DSI_D0_N - (12)
15 (13) GND - (14)
16 (15) DSI_D1_P - (16)
17 (17) DSI_D1_N - (18)
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/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
145 #define MIO37 37
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
193 #define MIO_GROUP_SPI1_2_SS0_PINS 37
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
205 #define MIO_GROUP_SDIO1_2_GRP_PINS 34, 35, 36, 37, 38, 39
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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/Zephyr-latest/dts/arm/atmel/
Ddma_atmel_same70.h3 * SPDX-License-Identifier: Apache-2.0
46 #define DMA_PERID_AES_TX 37
49 #define DMA_PERID_TC0_RX 40
Ddma_atmel_samv71.h3 * SPDX-License-Identifier: Apache-2.0
47 #define DMA_PERID_AES_TX 37
50 #define DMA_PERID_TC0_RX 40
/Zephyr-latest/samples/subsys/nvs/
Dsample.yaml10 - nrf52dk/nrf52832
15 - "Id: 1, Address: 192.168.1.1"
16 - "Id: 2, Key: ff fe fd fc fb fa f9 f8"
17 - "Id: 3, Reboot_counter: (.*)"
18 - "Id: 4, Data: DATA"
19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
20 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 \
21 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dr8a779f0_cpg_mssr.h4 * SPDX-License-Identifier: Apache-2.0
50 #define R8A779F0_CLK_SD0 37
53 #define R8A779F0_CLK_MSO 40
Dr8a7795_cpg_mssr.h4 * SPDX-License-Identifier: Apache-2.0
50 #define R8A7795_CLK_RPCD2 37
53 #define R8A7795_CLK_HDMI 40
Desp32s3_clock.h4 * SPDX-License-Identifier: Apache-2.0
85 #define ESP32_GDMA_MODULE 37
88 #define ESP32_MODULE_MAX 40
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h4 * SPDX-License-Identifier: Apache-2.0
47 #define FROM_CPU_INTR1_SOURCE 37
50 #define ASSIST_DEBUG_INTR_SOURCE 40
54 /* RISC-V supports priority values from 1 (lowest) to 15.
55 * As interrupt controller for Xtensa and RISC-V is shared, this is
Desp-esp32c3-intmux.h4 * SPDX-License-Identifier: Apache-2.0
47 #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37
50 #define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40
73 /* RISC-V supports priority values from 1 (lowest) to 15.
74 * As interrupt controller for Xtensa and RISC-V is shared, this is
/Zephyr-latest/tests/bluetooth/qualification/
DICS_Zephyr_Bluetooth_Host.bqw1 <?xml version="1.0" encoding="utf-8"?>
2 <Qualification xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2…
5 …<Product Name="Zephyr Host" Description="host" Model="main" Website="" PublishDate="2024-11-26T00:…
13 <Feature>GAP 37b/1</Feature>
24 <Feature>GAP 37b/6</Feature>
44 <Feature>GAP 37c/2</Feature>
45 <Feature>GAP 37/7</Feature>
54 <Feature>GAP 37a/4</Feature>
64 <Feature>GAP 37/3a</Feature>
69 <Feature>GAP 37a/6</Feature>
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/Zephyr-latest/soc/ti/lm3s6965/
Dsoc.h2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for
61 #define IRQ_I2C1 37
64 #define IRQ_RESERVED4 40
/Zephyr-latest/boards/ti/common/
Dboosterpack_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "ti,boosterpack-header";
10 #gpio-cells = <2>;
11 gpio-map = <2 0 &gpio0 23 0>,
35 <37 0 &gpio0 19 0>,
38 <40 0 &gpio0 7 0>;
/Zephyr-latest/soc/arm/beetle/
Dsoc_irq.h4 * SPDX-License-Identifier: Apache-2.0
44 #define IRQ_LLCC_TXDMAL_DONE 37 /* Cordio */
47 #define IRQ_LLCC_RXDMAH_DONE 40 /* Cordio */
/Zephyr-latest/drivers/dai/intel/alh/
Dalh_map.h4 * SPDX-License-Identifier: Apache-2.0
12 * Stream ID -> DMA Handshake map
13 * -1 identifies invalid handshakes/streams
16 -1, /* 0 - INVALID */
17 -1, /* 1 - INVALID */
18 -1, /* 2 - INVALID */
19 -1, /* 3 - INVALID */
20 -1, /* 4 - INVALID */
21 -1, /* 5 - INVALID */
22 -1, /* 6 - INVALID */
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