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/Zephyr-latest/tests/subsys/dsp/basicmath/src/
Dq7.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
47 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7, 47, in_com1, in_com2, ref_add, 47);
48 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7, possat, in_maxpos, in_maxpos, ref_add_possat, 33);
49 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7, negsat, in_maxneg, in_maxneg, ref_add_negsat, 33);
81 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7_in_place, 47, in_com1, in_com2, ref_add, 47);
83 ref_add_possat, 33);
85 ref_add_negsat, 33);
116 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_sub_q7, 47, in_com1, in_com2, ref_sub, 47);
117 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_sub_q7, possat, in_maxpos, in_maxneg, ref_sub_possat, 33);
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-rp2350b-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "rpi-pico-rp2350-pinctrl-common.h"
12 /* RP2350B is in a QFN-80 package, and extends the set of available pins
18 #define SPI0_CSN_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_SPI)
32 #define SPI1_TX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_SPI)
37 #define UART0_RX_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_UART)
51 #define UART1_RX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_UART)
56 #define I2C0_SCL_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_I2C)
70 #define I2C1_SCL_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_I2C)
75 #define PWM_8B_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PWM)
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Desp32s3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
71 #define I2C0_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
99 #define I2C0_SCL_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
162 #define I2C0_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
190 #define I2C0_SDA_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
253 #define I2C1_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
281 #define I2C1_SCL_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
344 #define I2C1_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
372 #define I2C1_SDA_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
435 #define I2S0_I_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
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Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
44 #define SMARTBOND_FUNC_PDM_CLK 33
58 #define SMARTBOND_FUNC_LCD_SPI_CLK 47
Desp32c6-gpio-sigmap.h4 * SPDX-License-Identifier: Apache-2.0
64 #define ESP_CPU_GPIO_IN5 33
65 #define ESP_CPU_GPIO_OUT5 33
86 #define ESP_PARL_RX_DATA0 47
87 #define ESP_PARL_TX_DATA0 47
Desp32c2-gpio-sigmap.h4 * SPDX-License-Identifier: Apache-2.0
58 #define ESP_CPU_GPIO_IN5 33
59 #define ESP_CPU_GPIO_OUT5 33
67 #define ESP_LEDC_LS_SIG_OUT2 47
Dambiq-apollo3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
243 #define ADCSE5_P33 APOLLO3_PINMUX(33, 0)
244 #define NCE33_P33 APOLLO3_PINMUX(33, 1)
245 #define XT32KHz_P33 APOLLO3_PINMUX(33, 2)
246 #define GPIO_P33 APOLLO3_PINMUX(33, 3)
247 #define BLEIF_CSN_P33 APOLLO3_PINMUX(33, 4)
248 #define UA0CTS_P33 APOLLO3_PINMUX(33, 5)
249 #define CTIM23_P33 APOLLO3_PINMUX(33, 6)
250 #define SWO_P33 APOLLO3_PINMUX(33, 7)
343 #define XT32KHz_P47 APOLLO3_PINMUX(47, 0)
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Dsi32-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
54 #define SI32_SIGNAL_CMP0A 33
74 #define SI32_SIGNAL_SPI1_MISO 47
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
141 #define MIO33 33
155 #define MIO47 47
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
196 #define MIO_GROUP_SPI1_3_GRP_PINS 46, 47, 48
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
206 #define MIO_GROUP_SDIO1_3_GRP_PINS 46, 47, 48, 49, 50, 51
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
16 compatible = "zephyr,lvgl-pointer-input";
18 swap-xy;
19 invert-y;
25 gt911_lcd_par_s035: gt911-lcd_par_s035@5d {
28 irq-gpios = <&nxp_lcd_8080_connector 9 GPIO_ACTIVE_HIGH>;
29 reset-gpios = <&nxp_lcd_8080_connector 11 GPIO_ACTIVE_LOW>;
35 #address-cells = <1>;
36 #size-cells = <0>;
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/Zephyr-latest/drivers/dai/intel/alh/
Dalh_map.h4 * SPDX-License-Identifier: Apache-2.0
12 * Stream ID -> DMA Handshake map
13 * -1 identifies invalid handshakes/streams
16 -1, /* 0 - INVALID */
17 -1, /* 1 - INVALID */
18 -1, /* 2 - INVALID */
19 -1, /* 3 - INVALID */
20 -1, /* 4 - INVALID */
21 -1, /* 5 - INVALID */
22 -1, /* 6 - INVALID */
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/Zephyr-latest/samples/subsys/nvs/
Dsample.yaml10 - nrf52dk/nrf52832
15 - "Id: 1, Address: 192.168.1.1"
16 - "Id: 2, Key: ff fe fd fc fb fa f9 f8"
17 - "Id: 3, Reboot_counter: (.*)"
18 - "Id: 4, Data: DATA"
19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
20 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 \
21 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
/Zephyr-latest/dts/arm/atmel/
Ddma_atmel_samv71.h3 * SPDX-License-Identifier: Apache-2.0
43 #define DMA_PERID_SSC_RX 33
57 #define DMA_PERID_I2SC1_RX_L 47
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dr8a779f0_cpg_mssr.h4 * SPDX-License-Identifier: Apache-2.0
46 #define R8A779F0_CLK_ZB3 33
60 #define R8A779F0_CLK_DBGSOC_HSC 47
Dr8a7795_cpg_mssr.h4 * SPDX-License-Identifier: Apache-2.0
46 #define R8A7795_CLK_SSP2 33
62 #define R8A7795_CLK_S0D2 47
Dnxp_s32k146_clock.h4 * SPDX-License-Identifier: Apache-2.0
41 #define NXP_S32_BUS_RUN_CLK 33U
55 #define NXP_S32_FTM4_EXT_CLK 47U
/Zephyr-latest/dts/bindings/gpio/
Dambiq-header.yaml2 # SPDX-License-Identifier: Apache-2.0
13 VDD_MCU - VDD_MCU - GPIO22 22 GND -
14 VDD_EXT - VDD_EXT - GPIO23 23 GPIO24 24
15 nRST - GND - VDD_MCU - GND -
16 VDD_EXT - VDD_EXT - GND - GPIO64 64
17 VDD_5V - VDD_5V - GPIO61 61 GPIO65 65
18 GND - GND - GPIO63 63 GPIO66 66
19 GND - GPIO100 100 GPIO62 62 GPIO67 67
20 VDDH2 - GPIO97 97 GPIO47 47 GPIO68 68
31 GPIO12 12 GPIO36 36 GPIO10 10 GPIO33 33
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Dadi,sdp-120.yaml4 # SPDX-License-Identifier: Apache-2.0
9 120-pin SDP interface:
43 33 SPI_D2 SPORT_DT0 88
57 47 GPIO6 GPIO7 74
72 compatible: "adi,sdp-120"
74 include: [gpio-nexus.yaml, base.yaml]
Dst,dsi-lcd-qsh-030.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on QSH-030-01-F-D-A connector used as DSI LCD connector.
9 (1) GND - (2)
11 (5) DSI_CK_N - (6)
12 (7) GND - (8)
13 (9) DSI_D0_P - (10)
14 (11) DSI_D0_N - (12)
15 (13) GND - (14)
16 (15) DSI_D1_P - (16)
17 (17) DSI_D1_N - (18)
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/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi2 * Copyright (c) 2019-2020 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "arm,cmsdk-timer";
22 interrupts = <33 3>;
29 interrupt-names = "rx", "tx", "rxtim", "err";
31 current-speed = <115200>;
37 interrupts = <45 3 46 3 47 3 49 3>;
38 interrupt-names = "rx", "tx", "rxtim", "err";
40 current-speed = <115200>;
44 compatible = "arm,cmsdk-gpio";
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/Zephyr-latest/drivers/gpio/
Dgpio_renesas_rz.h4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
13 #define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20)
14 #define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
44 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
45 47, 52, 56, 58, 63, 66, 70, 72, 76};
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c3-intmux.h4 * SPDX-License-Identifier: Apache-2.0
43 #define TG0_WDT_LEVEL_INTR_SOURCE 33
57 #define RSA_INTR_SOURCE 47
73 /* RISC-V supports priority values from 1 (lowest) to 15.
74 * As interrupt controller for Xtensa and RISC-V is shared, this is
/Zephyr-latest/samples/subsys/fs/zms/
DREADME.rst1 .. zephyr:code-sample:: zms
3 :relevant-api: zms_high_level_api
40 .. zephyr-app-commands::
41 :zephyr-app: samples/subsys/fs/zms
51 .. code-block:: console
53 *** Booting Zephyr OS build v3.7.0-2383-g624f75400242 ***
72 …24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44…
91 …24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44…
/Zephyr-latest/boards/nxp/rd_rw612_bga/dts/
Dgoworld_16880_lcm.overlay1 #include <zephyr/dt-bindings/spi/spi.h>
10 compatible = "zephyr,lvgl-pointer-input";
12 swap-xy;
13 invert-y;
19 nxp,swap-bytes;
21 nxp,timer0-ratio = <15>;
25 * - R125, R123, R12, R124, R15, R243, R239, R236, R233, R286, R246
27 * - R9, R11, R20, R19, R242, R241, R237, R235, R245
31 * -------------------------------
49 mipi-max-frequency = <23000000>;
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/Zephyr-latest/boards/m5stack/m5stack_atoms3/
Dm5stack_atoms3_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "m5stack_atoms3-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
22 zephyr,shell-uart = &usb_serial;
24 zephyr,code-partition = &slot0_partition;
26 zephyr,bt-hci = &esp32_bt_hci;
36 compatible = "gpio-keys";
48 compatible = "regulator-fixed";
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