Lines Matching +full:33 +full:- +full:47
4 * SPDX-License-Identifier: Apache-2.0
141 #define MIO33 33
155 #define MIO47 47
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
196 #define MIO_GROUP_SPI1_3_GRP_PINS 46, 47, 48
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
206 #define MIO_GROUP_SDIO1_3_GRP_PINS 46, 47, 48, 49, 50, 51
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
227 #define MIO_GROUP_CAN0_9_GRP_PINS 46, 47
235 #define MIO_GROUP_CAN1_6_GRP_PINS 32, 33
250 #define MIO_GROUP_UART0_9_GRP_PINS 46, 47
258 #define MIO_GROUP_UART1_6_GRP_PINS 32, 33
273 #define MIO_GROUP_I2C0_9_GRP_PINS 46, 47
280 #define MIO_GROUP_I2C1_5_GRP_PINS 32, 33
330 #define MIO_GROUP_GPIO0_33_GRP_PINS 33
344 #define MIO_GROUP_GPIO0_47_GRP_PINS 47
351 #define MIO_GROUP_USB0_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
352 #define MIO_GROUP_USB1_0_GRP_PINS 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t