| /Zephyr-latest/tests/kernel/timer/timer_api/src/ |
| D | timer_convert.c | 26 int precision; /* 32 or 64 */
50 TESTFUNC(ms, cyc, floor, 32)
52 TESTFUNC(ms, cyc, near, 32)
54 TESTFUNC(ms, cyc, ceil, 32)
56 TESTFUNC(ms, ticks, floor, 32)
58 TESTFUNC(ms, ticks, near, 32)
60 TESTFUNC(ms, ticks, ceil, 32)
62 TESTFUNC(us, cyc, floor, 32)
64 TESTFUNC(us, cyc, near, 32)
66 TESTFUNC(us, cyc, ceil, 32)
[all …]
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_dw_registers.h | 167 DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
168 DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32)
170 DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32)
171 DEFINE_MM_REG_READ(cmd_data, DW_IC_REG_DATA_CMD, 32)
173 DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32)
174 DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32)
176 DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32)
177 DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32)
179 DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32)
180 DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32)
[all …]
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| /Zephyr-latest/tests/subsys/shell/shell/ |
| D | testcase.yaml | 6 min_ram: 32
12 min_flash: 32
19 min_flash: 32
26 min_flash: 32
33 min_flash: 32
40 min_flash: 32
47 min_flash: 32
54 min_flash: 32
61 min_flash: 32
68 min_flash: 32
[all …]
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| /Zephyr-latest/tests/bsim/bluetooth/audio/test_scripts/ |
| D | gmap_unicast_ac_5.sh | 36 Execute_AC_5 32_1_gr 16_1_gs
37 Execute_AC_5 32_2_gr 16_2_gs
40 Execute_AC_5 32_1_gr 32_1_gs
41 Execute_AC_5 32_2_gr 32_2_gs
42 Execute_AC_5 48_1_gr 32_1_gs
43 Execute_AC_5 48_2_gr 32_2_gs
46 Execute_AC_5 48_3_gr 32_1_gs
47 Execute_AC_5 48_4_gr 32_2_gs
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| D | gmap_unicast_ac_11_i.sh | 35 Execute_AC_11_I 32_1_gr 16_1_gs
36 Execute_AC_11_I 32_2_gr 16_2_gs
39 Execute_AC_11_I 32_1_gr 32_1_gs
40 Execute_AC_11_I 32_2_gr 32_2_gs
41 Execute_AC_11_I 48_1_gr 32_1_gs
42 Execute_AC_11_I 48_2_gr 32_2_gs
45 Execute_AC_11_I 48_3_gr 32_1_gs
46 Execute_AC_11_I 48_4_gr 32_2_gs
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| D | gmap_unicast_ac_3.sh | 36 Execute_AC_3 32_1_gr 16_1_gs
37 Execute_AC_3 32_2_gr 16_2_gs
40 Execute_AC_3 32_1_gr 32_1_gs
41 Execute_AC_3 32_2_gr 32_2_gs
42 Execute_AC_3 48_1_gr 32_1_gs
43 Execute_AC_3 48_2_gr 32_2_gs
46 Execute_AC_3 48_3_gr 32_1_gs
47 Execute_AC_3 48_4_gr 32_2_gs
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| D | gmap_unicast_ac_8_i.sh | 35 Execute_AC_8_I 32_1_gr 16_1_gs
36 Execute_AC_8_I 32_2_gr 16_2_gs
39 Execute_AC_8_I 32_1_gr 32_1_gs
40 Execute_AC_8_I 32_2_gr 32_2_gs
41 Execute_AC_8_I 48_1_gr 32_1_gs
42 Execute_AC_8_I 48_2_gr 32_2_gs
45 Execute_AC_8_I 48_3_gr 32_1_gs
46 Execute_AC_8_I 48_4_gr 32_2_gs
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| D | gmap_unicast_ac_11_ii.sh | 39 Execute_AC_11_II 32_1_gr 16_1_gs
40 Execute_AC_11_II 32_2_gr 16_2_gs
43 Execute_AC_11_II 32_1_gr 32_1_gs
44 Execute_AC_11_II 32_2_gr 32_2_gs
45 Execute_AC_11_II 48_1_gr 32_1_gs
46 Execute_AC_11_II 48_2_gr 32_2_gs
49 Execute_AC_11_II 48_3_gr 32_1_gs
50 Execute_AC_11_II 48_4_gr 32_2_gs
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| D | gmap_unicast_ac_7_ii.sh | 39 Execute_AC_7_II 32_1_gr 16_1_gs
40 Execute_AC_7_II 32_2_gr 16_2_gs
43 Execute_AC_7_II 32_1_gr 32_1_gs
44 Execute_AC_7_II 32_2_gr 32_2_gs
45 Execute_AC_7_II 48_1_gr 32_1_gs
46 Execute_AC_7_II 48_2_gr 32_2_gs
49 Execute_AC_7_II 48_3_gr 32_1_gs
50 Execute_AC_7_II 48_4_gr 32_2_gs
|
| D | gmap_unicast_ac_8_ii.sh | 39 Execute_AC_8_II 32_1_gr 16_1_gs
40 Execute_AC_8_II 32_2_gr 16_2_gs
43 Execute_AC_8_II 32_1_gr 32_1_gs
44 Execute_AC_8_II 32_2_gr 32_2_gs
45 Execute_AC_8_II 48_1_gr 32_1_gs
46 Execute_AC_8_II 48_2_gr 32_2_gs
49 Execute_AC_8_II 48_3_gr 32_1_gs
50 Execute_AC_8_II 48_4_gr 32_2_gs
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| /Zephyr-latest/drivers/spi/ |
| D | spi_dw_regs.h | 45 DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
46 DEFINE_MM_REG_READ(ctrlr0, DW_SPI_REG_CTRLR0, 32)
47 DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
48 DEFINE_MM_REG_WRITE(rxftlr, DW_SPI_REG_RXFTLR, 32)
49 DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 32)
50 DEFINE_MM_REG_READ(txftlr, DW_SPI_REG_TXFTLR, 32)
51 DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
52 DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
53 DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
56 DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 32)
[all …]
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| /Zephyr-latest/samples/drivers/clock_control_xec/ |
| D | README.rst | 9 This sample demonstrates configuring the 32KHz clock
20 GPIO221 alternate function 1 is 32KHZ_OUT and can be monitored on Assembly 6915 JP7 pin 5.
22 Internal Silicon 32KHz Oscillator jumper configuration
28 Dual-ended 32KHz Crystal jumper configuration
36 Remove jumper on JP121 to prevent U15 32KHz 50% duty waveform
39 External single-ended 32KHz waveform to MEC172x XTAL2 input
43 Jumper on JP2 1-2 connect external 32KHz signal to XTAL2
47 Jumper on JP121 pins 3-4 connect U15 32KHz output to
50 External single-ended 32KHz waveform to MEC172x 32KHZ_IN pin
58 Jumper on JP121 pins 1-2 connect U15 32KHz output to
[all …]
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| /Zephyr-latest/dts/bindings/clock/ |
| D | microchip,xec-pcr.yaml | 25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
33 description: 32 KHz clock source for peripherals
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
56 the measured 32KHz high and low pulse widths.
62 Minimum number of consecutive 32KHz pulses that pass all monitor tests
86 If the internal silicon 32KHz oscillator is not chosen as the source
87 for PLL and Periheral devices then disable the internal 32KHz
|
| /Zephyr-latest/samples/drivers/clock_control_xec/src/ |
| D | main.c | 28 LOG_INF("PCR Power Reset Status register(bit[10] is 32K_ACTIVE) = 0x%x", r); in pcr_clock_regs()
48 LOG_INF("32KHz clock source is XTAL"); in vbat_clock_regs()
51 " (external 32KHz waveform)"); in vbat_clock_regs()
57 LOG_INF("32KHz clock source is the Internal Silicon 32KHz OSC"); in vbat_clock_regs()
60 LOG_INF("32KHz clock domain uses the 32KHZ_IN pin(GPIO_0165 F1)"); in vbat_clock_regs()
62 LOG_INF("32KHz clock domain uses the 32KHz clock source"); in vbat_clock_regs()
65 LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM); in vbat_clock_regs()
88 LOG_INF("PLL 32K clock source is Internal Silicon OSC(VTR)"); in print_pll_clock_src()
90 LOG_INF("PLL 32K clock source is XTAL input(VTR)"); in print_pll_clock_src()
92 LOG_INF("PLL 32K clock source is 32KHZ_IN pin(VTR)"); in print_pll_clock_src()
[all …]
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| /Zephyr-latest/tests/unit/pot/ |
| D | log2ceil.cpp | 10 static constexpr uint8_t val = LOG2CEIL(32);
11 static constexpr uint8_t val64 = LOG2CEIL(42 + BIT64(32));
31 zassert_equal(32, LOG2CEIL(BIT(31) + 1)); in ZTEST()
32 zassert_equal(32, LOG2CEIL(UINT32_MAX)); in ZTEST()
33 zassert_equal(32, LOG2CEIL(BIT64(32))); in ZTEST()
34 zassert_equal(33, LOG2CEIL(BIT64(32) + 1)); in ZTEST()
41 zassert_equal(5, log2ceil(32)); in ZTEST()
43 zassert_equal(33, log2ceil(42 + BIT64(32))); in ZTEST()
|
| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_em.props | 5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
54 dcache=16384,32,2,a
56 icache=16384,32,2,a
|
| D | nsim_hs_mpuv6.props | 5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
21 mpu_regions=32
|
| D | nsim_em11d.props | 5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
55 dcache=16384,32,2,a
57 icache=16384,32,2,a
|
| D | nsim_em7d_v22.props | 5 nsim_isa_rgf_num_regs=32
8 nsim_isa_lpc_size=32
9 nsim_isa_pc_size=32
10 nsim_isa_addr_size=32
42 dcache=16384,32,2,a
44 icache=16384,32,2,a
|
| D | nsim_hs5x.props | 8 nsim_isa_rgf_num_regs=32
12 nsim_isa_pc_size=32
13 nsim_isa_addr_size=32
43 mmu_address_space=32
44 nsim_isa_number_of_interrupts=32
59 nsim_cluster_version=32
|
| /Zephyr-latest/dts/bindings/pwm/ |
| D | telink,b91-pwm.yaml | 19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
23 description: Enable 32K Source Clock for PWM Channel 0
27 description: Enable 32K Source Clock for PWM Channel 1
31 description: Enable 32K Source Clock for PWM Channel 2
35 description: Enable 32K Source Clock for PWM Channel 3
39 description: Enable 32K Source Clock for PWM Channel 4
43 description: Enable 32K Source Clock for PWM Channel 5
|
| D | microchip,xec-pwmbbled.yaml | 31 Clock source selection: 32 KHz is available in deep sleep.
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
47 enable-low-power-32k:
52 - 32KHz Core clock (32.768KHz)
54 PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED.
56 Property "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink
|
| /Zephyr-latest/samples/net/sockets/echo_server/ |
| D | overlay-ws-console.conf | 8 CONFIG_NET_SOCKETS_POLL_MAX=32
9 CONFIG_NET_MAX_CONN=32
10 CONFIG_NET_SOCKETS_TLS_MAX_CONTEXTS=32
12 CONFIG_ZVFS_OPEN_MAX=32
|
| /Zephyr-latest/samples/boards/espressif/flash_memory_mapped/src/ |
| D | main.c | 21 uint8_t buffer[32]; in main()
40 LOG_HEXDUMP_INF(mem_ptr, 32, "flash read using memory-mapped pointer"); in main()
42 LOG_INF("writing 32-bytes data using flash API"); in main()
44 for (int k = 0; k < 32; k++) { in main()
47 flash_write(flash_device, address, buffer, 32); in main()
51 flash_read(flash_device, address, buffer, 32); in main()
52 LOG_HEXDUMP_INF(buffer, 32, "flash read using flash API"); in main()
54 LOG_HEXDUMP_INF(mem_ptr, 32, "flash read using memory-mapped pointer"); in main()
56 if (memcmp(buffer, mem_ptr, 32) == 0) { in main()
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| /Zephyr-latest/soc/espressif/esp32s3/ |
| D | Kconfig | 24 If you use 16KB instruction cache rather than 32KB instruction cache,
30 bool "32KB"
65 bool "32 Bytes"
71 default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
85 If you use 32KB data cache rather than 64KB data cache,
86 the other 32KB will be added to the heap.
91 bool "32KB"
98 # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
130 bool "32 Bytes"
138 default 32 if ESP32S3_DATA_CACHE_LINE_32B
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