Home
last modified time | relevance | path

Searched +full:256 +full:kb (Results 1 – 25 of 215) sorted by relevance

123456789

/Zephyr-latest/soc/nuvoton/npcx/npcx7/
Dmpu_regions.c11 CONFIG_FLASH_BASE_ADDRESS & -KB(256),
13 #if CONFIG_FLASH_SIZE > 256
15 (CONFIG_FLASH_BASE_ADDRESS + KB(256)) & -KB(256),
/Zephyr-latest/dts/common/nordic/
Dnrf5340_cpuapp_partition.dtsi14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
Dnrf91xx_partition.dtsi14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
Dnrf54l15.dtsi14 /* 188 + 68 = 256KB */
31 /* 1428 + 96 = 1524KB */
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts103 * Total size : 256 KB
104 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors,
105 * 256 B pages
106 * Write size : up to 256 B (page size)
115 * Total size : 128 KB
116 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
117 * Write size : up to 256 B (page size)
126 * Total size : 64 KB
127 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
/Zephyr-latest/boards/st/nucleo_f756zg/
Dnucleo_f756zg.dts164 * 256KB for bootloader. This is too large but
169 reg = <0x00000000 DT_SIZE_K(256)>;
173 /* application image slot: 256KB */
176 reg = <0x00040000 DT_SIZE_K(256)>;
179 /* backup slot: 256KB */
182 reg = <0x00080000 DT_SIZE_K(256)>;
185 /* scratch slot: 256KB */
188 reg = <0x000C0000 DT_SIZE_K(256)>;
/Zephyr-latest/tests/drivers/flash/common/boards/
Dgd32a503v_eval.overlay13 /* Set 4KB of storage at the border of bank0(256KB) and bank1(128KB). */
/Zephyr-latest/boards/silabs/radio_boards/slwrb4250b/
Dslwrb4250b.dts49 /* Reserve 32 kB for the bootloader */
56 /* Reserve 94 kB for the application in slot 0 */
62 /* Reserve 94 kB for the application in slot 1 */
68 /* Reserve 30 kB for the scratch partition */
74 /* Set 6Kb of storage at the end of the 256Kb of flash */
/Zephyr-latest/boards/st/nucleo_h753zi/
Dnucleo_h753zi.dts213 /* 128KB for bootloader */
220 /* storage: 128KB for settings */
226 /* application image slot: 256KB */
229 reg = <0x00040000 DT_SIZE_K(256)>;
232 /* backup slot: 256KB */
235 reg = <0x00080000 DT_SIZE_K(256)>;
238 /* swap slot: 128KB */
/Zephyr-latest/boards/st/nucleo_f429zi/
Dnucleo_f429zi.dts198 /* 32KB for bootloader */
217 /* application image slot: 256KB */
220 reg = <0x00020000 DT_SIZE_K(256)>;
223 /* backup slot: 256KB */
226 reg = <0x00060000 DT_SIZE_K(256)>;
229 /* swap slot: 128KB */
/Zephyr-latest/boards/ezurio/bl5340_dvk/
Dbl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi43 * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
44 * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
45 * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
/Zephyr-latest/boards/nxp/lpcxpresso11u68/support/
Dopenocd.cfg15 # NXP LPC11U68 Cortex-M0 with 256kB flash and 32kB + 4kB SRAM.
/Zephyr-latest/boards/st/nucleo_h743zi/
Dnucleo_h743zi.dts238 /* 128KB for bootloader */
245 /* storage: 128KB for settings */
251 /* application image slot: 256KB */
254 reg = <0x00040000 DT_SIZE_K(256)>;
257 /* backup slot: 256KB */
260 reg = <0x00080000 DT_SIZE_K(256)>;
263 /* swap slot: 128KB */
/Zephyr-latest/dts/bindings/interrupt-controller/
Darm,gic-v3.yaml23 redistributor-stride = <0x40000>; /* 256kB stride */
43 memory. Must be a multiple of 64kB. Required if the distance between
44 redistributors is not the default 128kB.
/Zephyr-latest/drivers/flash/
Dflash_gd32_v2.c21 * Bank0 holds the first 512KB, bank1 is used give capacity for reset.
28 #define GD32_NV_FLASH_V2_BANK0_SIZE KB(512)
30 #define GD32_NV_FLASH_V2_BANK1_SIZE (SOC_NV_FLASH_SIZE - KB(512))
37 * Bank0 holds the first 256KB, bank1 is used give capacity for reset.
38 * The page size is 1KB for all banks.
40 #if (PRE_KB(256) >= SOC_NV_FLASH_SIZE)
44 #define GD32_NV_FLASH_V2_BANK0_SIZE KB(256)
46 #define GD32_NV_FLASH_V2_BANK1_SIZE (SOC_NV_FLASH_SIZE - KB(256))
Dflash_stm32f7x.c229 {.pages_count = 2, .pages_size = KB(32)},
234 {.pages_count = 4, .pages_size = KB(16)},
240 {.pages_count = 4, .pages_size = KB(16)},
241 {.pages_count = 1, .pages_size = KB(64)},
242 {.pages_count = 3, .pages_size = KB(128)},
247 {.pages_count = 4, .pages_size = KB(32)},
248 {.pages_count = 1, .pages_size = KB(128)},
249 {.pages_count = 3, .pages_size = KB(256)},
255 {.pages_count = 4, .pages_size = KB(32)},
256 {.pages_count = 1, .pages_size = KB(128)},
[all …]
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l233rc.dtsi35 reg = <0x08000000 DT_SIZE_K(256)>;
38 * From other GD32 DataSheets, we can find 1KB page normally have a
41 * time to 4 times of 1KB page.
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx7m7fc.dtsi13 * Reallocate the last 64 KB of code RAM for use as data RAM
14 * because the internal flash size is 512 KB.
16 reg = <0x10070000 DT_SIZE_K(256)>;
/Zephyr-latest/boards/realtek/rts5912_evb/doc/
Dindex.rst14 - 384 KB SRAM
15 - 64 KB ROM
16 - 512 KB Flash(MCM)
17 - 256 B Battery SRAM
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_f1.dts30 /* Reserve first 512kB of shared memory for ADSP. */
32 /* Reset section must always be at 0 and at least 1kB. */
44 reg = <0x840000 DT_SIZE_K(256)>;
/Zephyr-latest/include/zephyr/arch/arm/mpu/
Darm_mpu_v7m.h81 #define REGION_256B REGION_SIZE(256B)
83 #define REGION_1K REGION_SIZE(1KB)
84 #define REGION_2K REGION_SIZE(2KB)
85 #define REGION_4K REGION_SIZE(4KB)
86 #define REGION_8K REGION_SIZE(8KB)
87 #define REGION_16K REGION_SIZE(16KB)
88 #define REGION_32K REGION_SIZE(32KB)
89 #define REGION_64K REGION_SIZE(64KB)
90 #define REGION_128K REGION_SIZE(128KB)
91 #define REGION_256K REGION_SIZE(256KB)
[all …]
/Zephyr-latest/soc/espressif/esp32c2/
Dmemory.h7 /* SRAM0 (16kB) memory */
11 /* SRAM1 (256kB) memory */
16 /* ICache size is fixed to 16KB on ESP32-C2 */
/Zephyr-latest/drivers/i3c/
DKconfig.stm3233 during a single transfer. 2KB guarantees enough heap size for sending 256
/Zephyr-latest/drivers/interrupt_controller/
Dintc_intel_vtd.h12 /* We don't care about int_idx[15], since the size is fixed to 256,
45 /* The table must be 4KB aligned, which is exactly 256 entries.
46 * And since we allow only 256 entries as a maximum: let's align to it.
48 #define IRTE_NUM 256
49 #define IRTA_SIZE 7 /* size = 2^(X+1) where IRTA_SIZE is X 2^8 = 256 */
51 #define QI_NUM 256 /* Which is the minimal number we can set for the queue */
52 #define QI_SIZE 0 /* size = 2^(X+8) where QI_SIZE is X: 2^8 = 256 */
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6e2bb3cfm.dtsi12 block-32kb-linear-end = <13>;
15 reg = <0x0 DT_SIZE_K(256)>;

123456789