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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-latest/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.esptool88 bool "120 MHz"
92 - Flash 120 MHz SDR mode is stable.
93 - Flash 120 MHz DDR mode is an experimental feature, it works when
98 increases or decreases by approximately 20 Celsius degrees (depending on the
102 bool "80 MHz"
104 bool "60 MHz"
106 bool "40 MHz"
108 bool "26 MHz"
111 bool "20 MHz"
119 This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
[all …]
/Zephyr-latest/tests/drivers/can/timing/
DKconfig16 - 20 kbit/s
33 - 20 MHz
34 - 40 MHz
35 - 80 MHz
/Zephyr-latest/boards/shields/mikroe_eth_click/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay12 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
23 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
/Zephyr-latest/subsys/lorawan/
DKconfig35 default 20
48 bool "Asia 923MHz Frequency band"
51 bool "Australia 915MHz Frequency band"
54 bool "China 470MHz Frequency band"
57 bool "China 779MHz Frequency band"
60 bool "Europe 433MHz Frequency band"
63 bool "Europe 868MHz Frequency band"
66 bool "South Korea 920MHz Frequency band"
69 bool "India 865MHz Frequency band"
72 bool "North America 915MHz Frequency band"
[all …]
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/doc/hardware/peripherals/
Despi.rst14 lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz)
27 https://downloadmirror.intel.com/27055/327432%20espi_base_specification%20R1-5.pdf
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c18 #define DIO20_PIN 20
42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
64 * least 20 ns and ten wait at least 35 us. in CC1352R1_LAUNCHXL_wakeUpExtFlash()
67 /* Toggle chip select for ~20ns to wake ext. flash */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-latest/boards/shields/mikroe_eth_click/
Dmikroe_eth_click.overlay13 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
/Zephyr-latest/boards/silabs/radio_boards/xg23_rb4210a/
Dboard.yml3 full_name: EFR32xG23 868-915 MHz 20 dBm (xG23-RB4210A)
Dxg23_rb4210a.yaml2 name: EFR32xG23 868-915 MHz 20 dBm Radio Board (xG23-RB4210A, BRD4210A)
/Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/
Dmain.c21 .frequency = MHZ(128),
26 .frequency = MHZ(320),
31 .frequency = MHZ(64),
40 .frequency = MHZ(16),
45 .frequency = MHZ(16),
50 .frequency = MHZ(16),
66 .frequency = MHZ(16),
67 .accuracy = 20,
71 .frequency = MHZ(19),
76 .frequency = MHZ(16),
[all …]
/Zephyr-latest/dts/bindings/power/
Dst,stm32wb0-pwr.yaml66 The SMPS clock, CLK_SMPS, comes from a 16 MHz source that
71 Setting this property to 2 results in CLK_SMPS = 8 MHz.
72 Setting this property to 4 results in CLK_SMPS = 4 MHz.
97 default: "20"
101 The default value of 20 mA corresponds to the maximal
113 - "20"
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
69 default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
/Zephyr-latest/tests/drivers/flash/common/boards/
Dnrf52840dk_spi_nor_wp_hold.overlay42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
51 e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb
52 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
Dnrf52840dk_spi_nor.overlay42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
49 e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb
50 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
/Zephyr-latest/tests/benchmarks/latency_measure/
Dtestcase.yaml27 # is achievable only if frequency is below 0x00FFFFFF (around 16MHz)
28 # 20 Ticks per secondes allows a frequency up to 335544300Hz (335MHz)
33 - CONFIG_SYS_CLOCK_TICKS_PER_SEC=20
/Zephyr-latest/boards/makerbase/mks_canable_v20/doc/
Dindex.rst79 By default system clock is driven by PLL clock at 160 MHz,
80 the PLL is driven by the 16 MHz high speed internal oscillator.
82 The FDCAN1 peripheral is driven by PLLQ, which has 80 MHz frequency.
158 …b.com/makerbase-mks/CANable-MKS/blob/main/User%20Manual/CANable%20V2.0/Makerbase%20CANable%20V2.0%…
161 ….com/makerbase-mks/CANable-MKS/blob/main/Hardware/MKS%20CANable%20V2.0/MKS%20CANable%20V2.0_001%20…
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
167 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168 * range is 9 <--> 18 MHz.
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
178 * 2. tTransitionWindow - 12 to 20 uSec
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
198 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
199 * range is 9 <--> 18 MHz.
201 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
[all …]
/Zephyr-latest/soc/mediatek/mt8xxx/
Dcpuclk.c13 * * power-on default is 26Mhz, confirmed with a hacked SOF that
15 * * The original driver has a 13Mhz mode too, but it doesn't work (it
16 * hits all the same code and data paths as 26MHz and acts as a
63 const struct { uint16_t mhz; bool pll; uint32_t pll_con2; } freqs[] = { member
73 * an OS timer driver yet. Use the 13 MHz timer hardware directly.
95 delay_us(20); in set_pll_power()
123 void mtk_adsp_set_cpu_freq(int mhz) in mtk_adsp_set_cpu_freq() argument
128 if (freqs[idx].mhz == mhz) { in mtk_adsp_set_cpu_freq()
133 if (idx == cur_idx || freqs[idx].mhz != mhz) { in mtk_adsp_set_cpu_freq()
138 /* Switch to PLL from 26Mhz */ in mtk_adsp_set_cpu_freq()
[all …]
/Zephyr-latest/dts/bindings/can/
Dti,tcan4x5x.yaml39 TCAN4x5x oscillator clock frequency in Hz (20MHz or 40MHz).
/Zephyr-latest/tests/boards/espressif/rtc_clk/
DREADME.rst55 Testing CPU frequency: 80 MHz
56 Testing CPU frequency: 160 MHz
57 Testing CPU frequency: 240 MHz
61 Testing CPU frequency: 40 MHz
62 Testing CPU frequency: 20 MHz
63 Testing CPU frequency: 10 MHz
64 Testing CPU frequency: 5 MHz
68 Testing RTC FAST CLK freq: 20000000 MHz
69 Testing RTC FAST CLK freq: 17500000 MHz
73 Testing RTC SLOW CLK freq: 136000 MHz
[all …]
/Zephyr-latest/soc/arm/beetle/
Dsoc_pll.h22 * - PLL_INPUTDIV [20:16]
27 * The Fin = 24Mhz on Beetle
33 * PLL_INPUTDIV = R[20:16] + 1

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