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/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
[all …]
Doa_tc6.h4 * SPDX-License-Identifier: Apache-2.0
21 #define OA_RESET_SWRESET BIT(0)
23 #define OA_CONFIG0_SYNC BIT(15)
24 #define OA_CONFIG0_RFA_ZARFE BIT(12)
25 #define OA_CONFIG0_PROTE BIT(5)
27 #define OA_STATUS0_RESETC BIT(6)
33 #define OA_IMASK0_TXPEM BIT(0)
34 #define OA_IMASK0_TXBOEM BIT(1)
35 #define OA_IMASK0_TXBUEM BIT(2)
36 #define OA_IMASK0_RXBOEM BIT(3)
[all …]
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
28 #define ADIN2111_RESET_SWRESET BIT(0)
33 #define ADIN2111_CONFIG0_SYNC BIT(15)
35 #define ADIN2111_CONFIG0_TXFCSVE BIT(14)
37 #define ADIN2111_CONFIG0_ZARFE BIT(12)
39 #define ADIN2111_CONFIG0_CSARFE BIT(13)
41 #define ADIN2111_CONFIG0_TXCTE BIT(9)
43 #define ADIN2111_CONFIG0_RXCTE BIT(8)
48 #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14)
50 #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13)
[all …]
/Zephyr-latest/drivers/spi/
Dspi_pw.h1 /* spi_pw.h - Penwell SPI driver definitions */
6 * SPDX-License-Identifier: Apache-2.0
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
59 /* SSP Baud rate sscr0[19:8] */
66 /* [19:8] 12 bits */
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
[all …]
/Zephyr-latest/drivers/can/
Dcan_sja1000_priv.h4 * SPDX-License-Identifier: Apache-2.0
31 #define CAN_SJA1000_ACR3 (19U)
41 #define CAN_SJA1000_EFF_ID3 (19U)
43 #define CAN_SJA1000_SFF_DATA (19U)
51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/memory-attr/
Dmemory-attr.h4 * SPDX-License-Identifier: Apache-2.0
20 #define DT_MEM_CACHEABLE BIT(0) /* cacheable */
21 #define DT_MEM_NON_VOLATILE BIT(1) /* non-volatile */
22 #define DT_MEM_OOO BIT(2) /* out-of-order */
23 #define DT_MEM_DMA BIT(3) /* DMA-able */
24 #define DT_MEM_UNKNOWN BIT(15) /* must be last */
33 #define DT_MEM_SW_ATTR_MASK GENMASK(19, 16)
36 #define DT_MEM_SW_ATTR_UNKNOWN BIT(19)
44 * See for example `include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h`
49 #define DT_MEM_ARCH_ATTR_UNKNOWN BIT(31)
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/drivers/usb/common/
Dusb_dwc2_hw.h5 * SPDX-License-Identifier: Apache-2.0
123 * used to get/set a bitfield consisting of only one bit.
158 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS BIT(USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS)
160 #define USB_DWC2_GAHBCFG_AHBSINGLE BIT(USB_DWC2_GAHBCFG_AHBSINGLE_POS)
162 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT BIT(USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS)
164 #define USB_DWC2_GAHBCFG_REMMEMSUPP BIT(USB_DWC2_GAHBCFG_REMMEMSUPP_POS)
166 #define USB_DWC2_GAHBCFG_PTXFEMPLVL BIT(USB_DWC2_GAHBCFG_PTXFEMPLVL_POS)
168 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL BIT(USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS)
170 #define USB_DWC2_GAHBCFG_DMAEN BIT(USB_DWC2_GAHBCFG_DMAEN_POS)
179 #define USB_DWC2_GAHBCFG_GLBINTRMASK BIT(USB_DWC2_GAHBCFG_GLBINTRMASK_POS)
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
40 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
39 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
47 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
[all …]
/Zephyr-latest/samples/drivers/adc/adc_sequence/boards/
Dlpcxpresso55s69_cpu0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
29 * - Connect LPADC0 CH4B signal to voltage between 0~3.3V (P18 pin 1)
33 * Channel 0 is used for differential mode, with 13 bit resolution
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
49 #define SCARH_ENABLE BIT(3)
50 #define SCARH_ADDR_BIT19 BIT(7)
53 * SCAR registers contain 20-bit addresses in three registers, with one set
61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Ddmic_regs_ace3x.h3 * SPDX-License-Identifier: Apache-2.0
13 #define DMICSYNC_SYNCPRD GENMASK(19, 0)
16 #define DMICSYNC_SYNCPU BIT(20)
19 #define DMICSYNC_SYNCGO BIT(23)
22 #define DMICSYNC_CMDSYNC BIT(24)
31 #define DMICLCTL_OFLEN BIT(4)
34 #define DMICLCTL_INTEN BIT(5)
37 #define DMICLCTL_SPA BIT(16)
40 #define DMICLCTL_CPA BIT(23)
43 #define DMICLCTL_INTSTS BIT(31)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
D_soc_inthandlers.h3 * SPDX-License-Identifier: Apache-2.0
12 * order (low bits first) and will return a mask of that bit that can
17 #include <xtensa/config/core-isa.h>
22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Ddmic_regs_ace2x.h1 /* SPDX-License-Identifier: Apache-2.0 */
15 #define DMICSYNC_SYNCPRD GENMASK(19, 0)
18 #define DMICSYNC_SYNCPU BIT(20)
21 #define DMICSYNC_SYNCGO BIT(23)
24 #define DMICSYNC_CMDSYNC BIT(24)
34 #define DMICLCTL_OFLEN BIT(4)
37 #define DMICLCTL_INTEN BIT(5)
40 #define DMICLCTL_SPA BIT(16)
43 #define DMICLCTL_CPA BIT(23)
46 #define DMICLCTL_INTSTS BIT(31)
[all …]
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.h3 * SPDX-License-Identifier: Apache-2.0
10 #define CDNS_HRS09_PHY_SW_RESET BIT(0)
11 #define CDNS_HRS09_PHY_INIT_COMP BIT(1)
12 #define CDNS_HRS09_EXT_WR_MODE BIT(3)
13 #define CDNS_HRS09_RDCMD_EN_BIT BIT(15)
14 #define CDNS_HRS09_RDDATA_EN_BIT BIT(16)
21 #define CDNS_HRS00_SWR BIT(0)
26 /* SRS09 - Present State Register */
27 #define CDNS_SRS09_STAT_DAT_BUSY BIT(2)
28 #define CDNS_SRS09_CI BIT(16)
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2024 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
14 * order (low bits first) and will return a mask of that bit that can
19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
34 #define TS_LOCAL_TSCTRL_NTK BIT(31)
37 #define TS_LOCAL_TSCTRL_IONTE BIT(30)
40 #define TS_LOCAL_TSCTRL_SIP BIT(8)
43 #define TS_LOCAL_TSCTRL_HHTSE BIT(7)
46 #define TS_LOCAL_TSCTRL_LWCS BIT(6)
49 #define TS_LOCAL_TSCTRL_ODTS BIT(5)
65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
[all …]
/Zephyr-latest/arch/x86/include/
Dkernel_arch_data.h3 * SPDX-License-Identifier: Apache-2.0
33 #define IV_SIMD_FP 19
41 * EFLAGS/RFLAGS definitions. (RFLAGS is just zero-extended EFLAGS.)
44 #define EFLAGS_IF BIT(9) /* interrupts enabled */
45 #define EFLAGS_DF BIT(10) /* Direction flag */
53 #define CR0_PG BIT(31) /* enable paging */
54 #define CR0_WP BIT(16) /* honor W bit even when supervisor */
56 #define CR4_PSE BIT(4) /* Page size extension (4MB pages) */
57 #define CR4_PAE BIT(5) /* enable PAE */
58 #define CR4_OSFXSR BIT(9) /* enable SSE (OS FXSAVE/RSTOR) */

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