Lines Matching +full:19 +full:- +full:bit
3 * SPDX-License-Identifier: Apache-2.0
10 #define CDNS_HRS09_PHY_SW_RESET BIT(0)
11 #define CDNS_HRS09_PHY_INIT_COMP BIT(1)
12 #define CDNS_HRS09_EXT_WR_MODE BIT(3)
13 #define CDNS_HRS09_RDCMD_EN_BIT BIT(15)
14 #define CDNS_HRS09_RDDATA_EN_BIT BIT(16)
21 #define CDNS_HRS00_SWR BIT(0)
26 /* SRS09 - Present State Register */
27 #define CDNS_SRS09_STAT_DAT_BUSY BIT(2)
28 #define CDNS_SRS09_CI BIT(16)
30 /* SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up) */
31 #define LEDC BIT(0)
32 #define DT_WIDTH BIT(1)
33 #define HS_EN BIT(2)
37 #define CDNS_SRS10_BP BIT(8)
51 #define CDNS_SRS11_ICE BIT(0)
52 #define CDNS_SRS11_ICS BIT(1)
53 #define CDNS_SRS11_SDCE BIT(2)
57 #define CDNS_SRS11_SRFA BIT(24)
58 #define CDNS_SRS11_SRCMD BIT(25)
59 #define CDNS_SRS11_SRDAT BIT(26)
64 * • 1111b - Reserved
65 * • 1110b - t_sdmclk*2(27+2)
66 * • 1101b - t_sdmclk*2(26+2)
74 #define CDNS_SRS12_CC BIT(0)
75 #define CDNS_SRS12_TC BIT(1)
76 #define CDNS_SRS12_EINT BIT(15)
100 /* V18SE is 0 for DS and HS, 1 for UHS-I */
101 #define CDNS_SRS15_V18SE BIT(19)
102 #define CDNS_SRS15_CMD23_EN BIT(27)
104 #define CDNS_SRS15_HV4E BIT(28)
106 #define CDNS_SRS15_BIT_AD_64 BIT(29)
107 #define CDNS_SRS15_PVE BIT(31)
125 #define CP_USE_PHONY_DQS_CMD(x) (x << 19)
130 #define CP_RD_DEL_SEL(x) ((x) << 19)
152 #define CDNS_HRS00_SWR BIT(0)
193 #define CDNS_SRS03_CMD_START BIT(31)
194 #define CDNS_SRS03_CMD_USE_HOLD_REG BIT(29)
203 #define CDNS_SRS03_DATA_PRSNT BIT(21)
204 #define CDNS_SRS03_CMD_IDX_CHK_EN BIT(20)
205 #define CDNS_SRS03_RESP_CRCCE BIT(19)
206 #define CDNS_SRS03_RESP_ERR BIT(7)
207 #define CDNS_SRS03_MULTI_BLK_READ BIT(5)
208 #define CDNS_SRS03_CMD_READ BIT(4)
224 #define CDNS_SRS03_DMA_EN BIT(0)
225 #define CDNS_SRS03_BLK_CNT_EN BIT(1)
227 /* HRS07 - IO Delay Information Register */
232 /* HRS09 - PHY Control and Status Register */
235 /* HRS10 - Host Controller SDCLK start point adjustment */
257 #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - 1)
260 #define OCR_POWERUP BIT(31)
261 #define OCR_HCS BIT(30)
263 #define OCR_3_5_3_6 BIT(23)
264 #define OCR_3_4_3_5 BIT(22)
265 #define OCR_3_3_3_4 BIT(21)
266 #define OCR_3_2_3_3 BIT(20)
267 #define OCR_3_1_3_2 BIT(19)
268 #define OCR_3_0_3_1 BIT(18)
269 #define OCR_2_9_3_0 BIT(17)
270 #define OCR_2_8_2_9 BIT(16)
271 #define OCR_2_7_2_8 BIT(15)
274 #define OCR_VDD_MIN_1V7 BIT(7)
276 #define MMC_RSP_48 BIT(0)
277 #define MMC_RSP_136 BIT(1) /* 136 bit response */
278 #define MMC_RSP_CRC BIT(2) /* expect valid crc */
279 #define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
280 #define MMC_RSP_BUSY BIT(4) /* device may be busy */
302 #define PART_CFG_BOOT_PARTITION1_ENABLE BIT(3)
312 #define MMC_BOOT_MODE_HS_TIMING BIT(3)
316 #define EXTCSD_SET_BITS BIT(24)
328 #define STATUS_READY_FOR_DATA BIT(8)
329 #define STATUS_SWITCH_ERROR BIT(7)
346 #define VHS_2_7_3_6_V BIT(8)
348 #define SD_SCR_BUS_WIDTH_1 BIT(8)
349 #define SD_SCR_BUS_WIDTH_4 BIT(10)
352 #define ADMA_DESC_ATTR_VALID BIT(0)
353 #define ADMA_DESC_ATTR_END BIT(1)
354 #define ADMA_DESC_ATTR_INT BIT(2)
355 #define ADMA_DESC_ATTR_ACT1 BIT(4)
356 #define ADMA_DESC_ATTR_ACT2 BIT(5)
495 /* 8 bit attribute */
501 /* lower 32 bits for buffer (64 bit addressing) */
503 /* higher 32 bits for buffer (64 bit addressing) */