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/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
[all …]
Dcan_sja1000_priv.h4 * SPDX-License-Identifier: Apache-2.0
29 #define CAN_SJA1000_ACR1 (17U)
39 #define CAN_SJA1000_XFF_ID1 (17U)
51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
59 #define CAN_SJA1000_CMR_AT BIT(1)
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
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/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
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Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_vci.h4 * SPDX-License-Identifier: Apache-2.0
22 #define MCHP_VCI_VCI_OVRD_IN_HI BIT(8)
23 #define MCHP_VCI_VCI_OUT_HI BIT(9)
24 #define MCHP_VCI_FW_CTRL_EN BIT(10)
25 #define MCHP_VCI_FW_EXT_SEL BIT(11)
26 #define MCHP_VCI_FILTER_BYPASS BIT(12)
27 #define MCHP_VCI_WEEK_ALARM BIT(16)
28 #define MCHP_VCI_RTC_ALARM BIT(17)
29 #define MCHP_VCI_SYS_PWR_PRES BIT(18)
42 #define MCHP_VCI_LER_WEEK_ALARM BIT(16)
[all …]
/Zephyr-latest/dts/bindings/dma/
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
30 0x1: Half-word (16 bits)
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
[all …]
/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_boot.h3 * SPDX-License-Identifier: Apache-2.0
46 #define DSPCS_CTL_SPA BIT(0)
47 #define DSPCS_CTL_CPA BIT(8)
49 #define DSPBR_BCTL_BYPROM BIT(0)
50 #define DSPBR_BCTL_WAITIPCG BIT(16)
51 #define DSPBR_BCTL_WAITIPPG BIT(17)
53 #define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12)
54 #define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13)
55 #define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14)
56 #define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Dadsp_boot.h3 * SPDX-License-Identifier: Apache-2.0
46 #define DSPCS_CTL_SPA BIT(0)
47 #define DSPCS_CTL_CPA BIT(8)
49 #define DSPBR_BCTL_BYPROM BIT(0)
50 #define DSPBR_BCTL_WAITIPCG BIT(16)
51 #define DSPBR_BCTL_WAITIPPG BIT(17)
53 #define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12)
54 #define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13)
55 #define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14)
56 #define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32mp1_reset.h4 * SPDX-License-Identifier: Apache-2.0
11 * Pack RCC register offset and bit in one 32-bit value.
13 * 5 LSBs are used to keep bit number in 32-bit RCC register.
18 * @param bit Reset bit
20 #define STM32_RESET(bus, bit) \ argument
21 (((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit))
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_boot.h3 * SPDX-License-Identifier: Apache-2.0
47 #define DSPCS_CTL_SPA BIT(0)
48 #define DSPCS_CTL_CPA BIT(8)
50 #define DSPBR_BCTL_BYPROM BIT(0)
51 #define DSPBR_BCTL_WAITIPCG BIT(16)
52 #define DSPBR_BCTL_WAITIPPG BIT(17)
54 #define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12)
55 #define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13)
56 #define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14)
57 #define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
D_soc_inthandlers.h3 * SPDX-License-Identifier: Apache-2.0
12 * order (low bits first) and will return a mask of that bit that can
17 #include <xtensa/config/core-isa.h>
22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/intel/intel_socfpga/common/
Dsocfpga_system_manager.h2 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
4 * SPDX-License-Identifier: Apache-2.0
40 #define IDLE_DATA_LWSOC2FPGA BIT(0)
41 #define IDLE_DATA_SOC2FPGA BIT(4)
44 #define SYSMGR_ECC_OCRAM_MASK BIT(1)
45 #define SYSMGR_ECC_DDR0_MASK BIT(16)
46 #define SYSMGR_ECC_DDR1_MASK BIT(17)
/Zephyr-latest/dts/bindings/adc/
Dmaxim,max11105.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Maxim Integrated 1 channel 12 bit 2 Msps SPI ADC
8 include: maxim,max11102-17-base.yaml
Dmaxim,max11110.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Maxim Integrated 1 channel 10 bit 2 Msps SPI ADC
8 include: maxim,max11102-17-base.yaml
Dmaxim,max11115.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Maxim Integrated 1 channel 8 bit 2 Msps SPI ADC
8 include: maxim,max11102-17-base.yaml
Dmaxim,max11116.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Maxim Integrated 1 channel 8 bit 3 Msps SPI ADC
8 include: maxim,max11102-17-base.yaml
Dmaxim,max11117.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Maxim Integrated 1 channel 10 bit 3 Msps SPI ADC
8 include: maxim,max11102-17-base.yaml
/Zephyr-latest/soc/cdns/sample_controller32/include/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
14 * order (low bits first) and will return a mask of that bit that can
19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/renesas/rzt2m/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
16 #define CNTCR_EN BIT(0)
17 #define CNTCR_HDBG BIT(1)
20 #define PRCRS_CLK BIT(0)
21 #define PRCRS_LPC_RESET BIT(1)
22 #define PRCRS_GPIO BIT(2)
23 #define PRCRS_SYS_CTRL BIT(3)
25 /* Non-safety area protect register */
26 #define PRCRN_PRC0 BIT(0)
27 #define PRCRN_PRC1 BIT(1)
[all …]

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