1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ 8 9 #define DSPCS_REG 0x178d00 10 11 struct dspcs { 12 /* 13 * DSPCSx 14 * DSP Core Shim 15 * 16 * These registers are added by Intel outside of the Tensilica Core for general operation 17 * control, such as reset, stall, power gating, clock gating etc. 18 * Note: These registers are accessible through the host space or DSP space depending on 19 * ownership, as governed by SAI and RS. 20 */ 21 struct { 22 uint32_t cap; 23 uint32_t ctl; 24 } capctl[5]; 25 uint32_t unused0[6]; 26 27 /* 28 * DSPBRx 29 * DSP Boot / Recovery 30 * 31 * These registers are added by Intel outside of the Tensilica Core for boot / recovery 32 * control, such as boot path, watch dog timer etc. 33 */ 34 struct { 35 uint32_t brcap; 36 uint32_t wdtcs; 37 uint32_t wdtipptr; 38 uint32_t unused1; 39 uint32_t bctl; 40 uint32_t baddr; 41 uint32_t battr; 42 uint32_t unused2; 43 } bootctl[5]; 44 }; 45 46 #define DSPCS_CTL_SPA BIT(0) 47 #define DSPCS_CTL_CPA BIT(8) 48 49 #define DSPBR_BCTL_BYPROM BIT(0) 50 #define DSPBR_BCTL_WAITIPCG BIT(16) 51 #define DSPBR_BCTL_WAITIPPG BIT(17) 52 53 #define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12) 54 #define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13) 55 #define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14) 56 #define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15) 57 #define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16) 58 59 #define DSPBR_WDT_RESUME BIT(8) 60 #define DSPBR_WDT_RESTART_COMMAND 0x76 61 62 #define DSPCS (*(volatile struct dspcs *)DSPCS_REG) 63 64 #endif /* ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ */ 65
