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/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
53 DEFINE_CORRELATE_TEST(14, 17);
58 DEFINE_CORRELATE_TEST(15, 17);
63 DEFINE_CORRELATE_TEST(16, 17);
66 DEFINE_CORRELATE_TEST(17, 15);
67 DEFINE_CORRELATE_TEST(17, 16);
68 DEFINE_CORRELATE_TEST(17, 17);
69 DEFINE_CORRELATE_TEST(17, 18);
70 DEFINE_CORRELATE_TEST(17, 33);
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/boards/snps/nsim/arc_classic/support/
Dnsim_sem_mpu_stack_guard.props5 nsim_isa_rgf_num_regs=32
8 nsim_isa_lpc_size=32
9 nsim_isa_pc_size=32
10 nsim_isa_addr_size=32
41 nsim_isa_number_of_external_interrupts=17
44 dcache=16384,32,2,a
46 icache=16384,32,2,a
63 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
Dnsim_sem.props5 nsim_isa_rgf_num_regs=32
8 nsim_isa_lpc_size=32
9 nsim_isa_pc_size=32
10 nsim_isa_addr_size=32
41 nsim_isa_number_of_external_interrupts=17
44 dcache=16384,32,2,a
46 icache=16384,32,2,a
63 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
Dmdb_sem_mpu_stack_guard.args1 -arcv2em
2 -core3
3 -rgf_num_banks=1
4 -rgf_num_wr_ports=1
5 -Xcode_density
6 -Xdiv_rem=radix2
7 -turbo_boost
8 -Xswap
9 -Xbitscan
10 -Xmpy_option=mpyd
[all …]
Dmdb_sem.args1 -arcv2em
2 -core3
3 -rgf_num_banks=1
4 -rgf_num_wr_ports=1
5 -Xcode_density
6 -Xdiv_rem=radix2
7 -turbo_boost
8 -Xswap
9 -Xbitscan
10 -Xmpy_option=mpyd
[all …]
/Zephyr-latest/dts/arm/ene/
Dkb1200.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-m4";
24 clock-frequency = <DT_FREQ_M(48)>;
29 compatible = "mmio-sram";
34 flash-controller@50100000 {
35 compatible = "ene,kb1200-flash-controller";
37 #address-cells = <1>;
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
125 #define MIO17 17
140 #define MIO32 32
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
179 #define MIO_GROUP_SPI0_1_SS2_PINS 32
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dnxp,lcd-8080.yaml2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,lcd-8080"
8 GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel).
9 These pins are exposed on a 32 pin connector. The pins have the
29 17-32 LCD 8080 interface D0 - D15
31 include: [gpio-nexus.yaml, base.yaml]
Dnxp,cam-44pins-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on NXP 44-pin board-to-board camera connector.
17 18 MIPI_CSI_DN1/D8 PWDN 17
24 32 DGND D3 31
31 compatible: "nxp,cam-44pins-connector"
33 include: [gpio-nexus.yaml, base.yaml]
/Zephyr-latest/dts/bindings/dma/
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
30 0x1: Half-word (16 bits)
[all …]
Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 config: A 32bit mask specifying the DMA channel configuration
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
[all …]
Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
30 -bit 9 : Peripheral Increment Address
33 -bit 10 : Memory Increment Address
36 -bit 11-12 : Peripheral data size
[all …]
/Zephyr-latest/dts/bindings/clock/
Despressif,esp32-rtc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,esp32-rtc"
8 include: [clock-controller.yaml, base.yaml]
14 fast-clk-src:
19 - 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3)
21 - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz
23 - 0
24 - 1
26 slow-clk-src:
31 - 0: ESP32_RTC_SLOW_CLK_SRC_RC_SLOW - 136 KHz (C3/S3) - 90 kHz (S2) - 150 kHz (ESP32)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Desp32-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
73 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
103 ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
161 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
191 ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
249 ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
279 ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
337 ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
367 ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
425 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsame5x.dtsi5 * SPDX-License-Identifier: Apache-2.0
13 compatible = "atmel,sam0-gmac";
16 interrupt-names = "gmac";
19 num-queues = <1>;
20 local-mac-address = [00 00 00 00 00 00];
24 compatible = "atmel,sam-mdio";
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "atmel,sam0-can";
36 interrupt-names = "int0", "int1";
[all …]
/Zephyr-latest/dts/x86/intel/
Dapollo_lake.dtsi2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/tcpc/
Dst,stm32-ucpd.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ST STM32 family USB Type-C / Power Delivery. The default values were
8 compatible: "st,stm32-ucpd"
10 include: [base.yaml, pinctrl-device.yaml]
22 psc-ucpdclk:
26 - 1
27 - 2
28 - 4
29 - 8
30 - 16
[all …]
/Zephyr-latest/dts/arm/st/wb0/
Dstm32wb0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32mp1_reset.h4 * SPDX-License-Identifier: Apache-2.0
11 * Pack RCC register offset and bit in one 32-bit value.
13 * 5 LSBs are used to keep bit number in 32-bit RCC register.
21 (((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit))
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
/Zephyr-latest/tests/drivers/build_all/display/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
13 #include <zephyr/dt-bindings/led/led.h>
14 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
23 gpio-controller;
25 #gpio-cells = <0x2>;
30 compatible = "zephyr,mipi-dbi-spi";
32 dc-gpios = <&test_gpio 0 0>;
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_ioapic_priv.h1 /* ioapic_priv.h - private IOAPIC APIs */
4 * Copyright (c) 2012-2015 Wind River Systems, Inc.
7 * SPDX-License-Identifier: Apache-2.0
16 #define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
40 /* Redirection table entry bits: upper 32 bit */
44 /* Redirection table entry bits: lower 32 bit */
52 * The 15th bits is in the first 32bits of RTE but since
55 #define IOAPIC_VTD_INDEX(index) (index << 17)
/Zephyr-latest/drivers/crypto/
Dcrypto_intel_sha_registers.h4 * SPDX-License-Identifier: Apache-2.0
40 uint32_t ba : 17;
97 uint32_t upper_length : 32;
112 uint32_t upper_length : 32;
140 uint32_t dwx : 32;
147 uint32_t dwx : 32;

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